Posted by Hélène Thibiéroz on May 22, 2012
As we all know 🙂 , Moore’s law has been governing the development of the semiconductor industry for 45 years. However, when entering the nanometer technology node, the industry faced three main key challenges:
-increasing gate leakage currents due to shrinking gate oxide thickness,
-decreasing the electron/hole mobilities caused by the increasing substrate doping concentration,
– increasing subthreshold leakage currents arising from the increasing substrate leakage.
In response, the semiconductor industry invented the strained silicon engineering technology to boost the mobilities and created the high-K metal gate stack to reduce the gate leakage currents. To mitigate the subthreshold leakage current, several approaches were pursued. Among them, the 3-D FinFET structures have shown very promising results. With the Intel’s last year announcement that Trigate transistor, a derivative of FinFET, will be used in their 22nm node, FinFET has entered the central stage, replacing our traditional planar MOSFET.
But now, the next question is how to design circuits with FinFETs ? What are the impacts to the conventional design methodologies? Are the EDA tools ready to cope with the new challenges that come with the 3-D transistor structure? In this post, I am interviewing Frank Lee to answer some of those concerns and discuss about FinFET general challenges and SYNOPSYS leading role in the EDA industry.
Frank is currently a VP of Engineering in the Analog/Mixed-Signal Group at Synopsys. He is responsible for the device modeling and circuit simulation R&D teams. Frank is a 22-year EDA veteran. He has broad EDA experiences that cover physical verification, RC extraction, clock tree synthesis, delay calculation, static timing analysis, physical synthesis, place and route, device modeling and circuit simulation. Frank received PhD in Electrical and Computer Engineering from Carnegie Mellon University.
A- The FinFET structure was proposed and prototyped by Prof. Tsu-Jae King and Chenming Hu’s research team at UC Berkeley in year 2000. Since then, there are a lot of research teams all over the world (UCB, IMEC, Intel, TSMC, Samsung to name a few) engaged in the study of the characteristics of FinFETs and the design and optimization of the 3-D transistor structure. As in planar CMOS technologies, one of the most important tools for these activities is the technology CAD. Our Sentaurus Process and Technology 3-D simulators have played a key role in helping the researchers advancing the understanding and the design of FinFET and its technology development in the past decade. In 2004 – 2006, Prof. Tsu-Jae King was with the Advanced Technology Group at Synopsys conducting advanced research. Numeral patents resulted from this collaboration. It should be noted that the patent “Integrated circuit on corrugated substrate” co-invented by Tsu-Jae and Synopsys Scientist Victor Moroz, has been widely adopted by the industry to manufacture integrated circuits based on FinFets. On the other front, our device modeling team was also very busy working with Prof. Chenming Hu to productize the BSIM-CMG model, one of the compact models for FinFET, into our circuit simulations to enable circuit designers to design with FInFETs. Recently, a book co-authored by my colleague Weidong Liu and Prof. Chenming Hu was published, detailing advanced modeling features of FinFETs. In addition to the core model, due to its 3-D nature, the modeling of the mechanical stress and the parasitic R and C have posed quite some challenges. In order to solve these issues, our TCAD and StarRC teams have been working very closely with our partners TSMC and Samsung to build the models and develop methodology that streamlines the stress modeling, RC extraction and circuit simulation flow. Due to its multi-fin nature, the driving strength of the FinFET is quantized. This imposes a challenge in circuit designs that relies on careful transistor sizing to achieve design goals. One good example is the embedded SRAM designs. In the planar CMOS technology, continuous transistor sizing is used to balance the read and write static noise margin. With FinFET, this is no longer available. New techniques have to be employed. Our Solution Group has been working on next generation SRAM compiler that can take full advantage of FinFET features.
Q- Synopsys is currently working with major design houses. Moving forward, do you see a large deployment and use of FinFet technology for low power designs and advanced process nodes? What are the main compelling factors?
A- One of the key features that differentiates FinFETs from the planar devices is that the subthreshold leakage current can be orders of magnitude smaller than the conventional devices. In fact, it is an industry consensus that planar CMOS technology will end at 20nm due to its inability to turn off the transistor (subthreshold leakage current). So FinFET is here to stay. It is not 20nm, it will be 14nm.
Since the subthreshold leakage current is much lower, you can also trade off subthreshold leakage current by lowering threshold voltage. And with that you can actually reduce the power supply while keeping the same performance. This has a big effect in terms of dynamic power consumption. For example if you can reduce the supply voltage from 1 volte to 0.7 volt, you can reduce the dynamic power consumption by 50% since the dynamic power consumption is proportional to the square of the power supply voltage.
Another distinguishing merit that FinFET offers is less variation. Random dopant fluctuation (RDF) in the nanometer planar MSEFT is one of reasons that causes variation in transistor characteristics. FinFET structure allows you to have an undoped body. This means that it is free from RDF.
Q- What are the possible bottlenecks and challenges? How is SYNOPSYS addressing those as a leading EDA provider?
A- FinFET is a new device structure, it requires a new device model to describe its behavior accurately for circuit designs. The upcoming CMC standard BSIM-CMG model is recognized as the solution to fulfill this need. We have worked with the Berkeley BSIM modeling team on the production of the CMG model in Synopsys circuit simulators HSPICE and CustomSim several years ago. In addition to the core model, due to its 3-D nature, the modeling of the mechanical stress and the parasitic R and C have posed quite some challenges. In order to solve these issues, our TCAD and StarRC teams have been working very closely with our partners TSMC and Samsung to build the models and develop methodology that streamlines the stress modeling, RC extraction and circuit simulation flow.
Another challenge is the support of double patterning technology in the layout tools. Our IC Compiler has been equipped with the capability to handle the need for double patterning. Depending on the architecture of the standard cells libraries, both the placer and router can handle the rules for double patterning effectively.
Due to the discrete nature of the fins, FinFET current driving capability is quantized. This presents a challenge for circuits that requires transistor sizing to optimize the design. One example is the SRAM design. In the planar CMOS technology, continuous transistor sizing is used to balance the read and write static noise margin. With FinFET, this is no longer available. New techniques have to be employed. Our Solution Group has been working on next generation SRAM compiler that can take full advantage of FinFET features.
Q- Why would you select SYNOPSYS today if you want to migrate your design toward FinFet technology? What differentiates SYNOPSYS from other EDA vendors?
A- Finfet technology is here to stay. It has a new 3-D structure. It requires new compact models, new RC parasitics, new design rules and new tools that can handle these changes. Working with our partners, Synopsys has developed a complete set of tools and methodology to enable circuit designers to tackle the challenges in designing the FinFET based circuits.
I hope you enjoyed Frank’s interview! As usual, your comments and feedback are welcome. Stay tuned for our next post as we would be talking in more depth with Professor Chenming Hu on FinFET technology 🙂