Posted by Hélène Thibiéroz on April 6, 2012
Just a small post as we all are back to our daily job duties and in catch-up mode 🙂
I attended SNUG Monday AMS technical sessions as well as our technology keynote on Finfet technology by Professor Chenming Hu. I also got the chance to meet a lot of our customers at our DVE event and discuss emerging trends and simulation needs for Analog and Mixed-Signal designs.
I am therefore currently working on several posts that I will be releasing in the incoming weeks:
– I attended a very interesting talk by AMD on AMS verification using UVM : “Universal Verification Methodology (UVM)-based Random Verification through VCS and CustomSim in Analog Mixed-signal Designs for Faster Coverage Closure”, by Warren Anderson, Ravi Ram (AMD), and Vijay Akkaraju (Synopsys). This paper presented our UVM methodology using Synopsys CustomSim-VCS solution and VerilogAMS. I will have a follow up interview with AMD on this topic as performance and innovation shown by this Synopsys flow are worth a specific post.
– The Wednesday technology keynote “3D FinFET – New Structure Extends the Life of the Transistor!” presented by Professor Chenming Lu was extremely interesting and received the highest ranking of all previous SNUG keynotes. Professor Hu provided insight into the driving factors behind these new transistors and how these transistors will enable the continued use of existing infrastructures of circuit and system designs, as well as device fabrication, for decades to come. Because Synopsys is the EDA leader on FinFet technology, I will have in a near future an interview with Professor Lu and our R&D experts to further expand on this technology and Synopsys initiative.
That’s it for now. ..HAPPY EASTER! Joyeuses Paques !