Posted by Hélène Thibiéroz on February 28, 2012
yes, an other field trip report 🙂 You may remember we held our HSPICE Special Interest Group event during DesignCon week. This event gives you an opportunity to talk with Synopsys HSPICE R&D personnel and hear what our customers have to say about using HSPICE in today’s most challenging designs.
The agenda was:Altera: “28nm MOSFET Aging Modeling and Simulation Using HSPICE MOSRA” Cavium: “HSPICE Signal Integrity Portfolio for High-Speed SERDES Channel Design” Micron:”Simulating IBIS 5.0 Power-aware Models using HSPICE Synopsys: “HSPICE for Signal Integrity: a Peek under the Hood”
It was a great success: we had a 27% increase in customer attendance vs. 2011 as well as 11 HIP partners exhibiting. Because I received extremely positive feedback from our audience on the format of this event and the topics we discussed, I wanted to give you more insights from an attendee/speaker angle. I therefore asked our Synopsoid Scott Wedge to share his experience as a speaker.
A little more about Scott.. He spent ten years as an analog/RF/AMS design engineer with Hughes Aircraft Company working on a variety of military and satellite communications systems. After receiving his Ph.D. from Caltech, he joined the Touchstone R&D team at EEsof (now Agilent-EEsof), where he helped pioneer many new high-frequency circuit simulation and analysis capabilities. Scott was director of IC design tool research at Tanner EDA before joining the HSPICE R&D team at Synopsys where he has worked for the past 10 years developing new simulation approaches for noise, jitter, and signal integrity.
Q- Scott, you presented HSPICE/HPP latest features. Based on our post-mortem analysis and my discussions with multiple customers, your presentation was really well received by the audience. Could you please tell us more about the content? Which features do you consider being a differentiator for HSPICE/HPP?
A- Thanks, Helene! Since the HSPICE SIG event coincided with DesignCon, we took the opportunity to emphasize the many capabilities in HSPICE for handling critical aspects of signal integrity analysis. There are some other good tools out there for SI, especially for linear link modeling, but HSPICE has the advantage of being the only SI simulator that is also the gold standard for chip simulation. The strengths we have for nonlinear simulation, including our multi-core HPP engine, combined with high-performance modeling for link components, set us apart. In my content I showed how we are combining these strengths to deliver our multi-edge StatEye analysis; an approach that uses the speed of statistical eye diagram methods, yet captures critical nonlinear effects, for an outstanding combination of speed and accuracy.
Q- What were the highlights of this year’s event? As an HSPICE R&D member and as an attendee, did you benefit from this event? What was your major take-away (besides having a three-course meal 🙂 )?
A- What is always a highlight for me at the HSPICE SIG events is seeing and talking with all the HIP partners – the HSPICE Integrator Program members. I get a big kick out of seeing all the ways HSPICE is combined with other excellent tools to solve a variety of problems. The science buff in me loves seeing the latest electromagnetic analysis tools, and how they are getting faster and more accurate for solving a variety of geometries – and extracting models – that are very important for circuit and system design. The EE in me loves seeing the Design Environment tools – those that run HSPICE under the hood – how they make the designer more productive, and how they handle all the data and test benches that are crucial in modern design. The mathematician and computer buff in me loves seeing the behavioral modeling solutions used with HSPICE, such as IBIS and IBIS-AMI, and how they streamline the design and verification flows. The highlight was talking with customers that use HSPICE with the HIP tools, and all the amazing engineering solutions they are coming up with.
Q- How do you think this event could be improved?
A- I had such a good time, and the event was so well put together, with such excellent food and drink, it would be hard to improve upon. One thing: it was impossible to talk with all the people I had hoped to, and it was difficult connecting with them again at DesignCon with everyone’s busy schedules. In hindsight it would have been nice to have also had a Synopsys HSPICE exhibit at DesignCon, where HSPICE users and developers could connect and share additional information informally without the time constraints necessary for the SIG event.
Q- Based on the audience, which hot topics would you select for our next event?
A- Based on questions I had afterwards, there was a lot of interest in our new transient noise analysis solutions, and how they apply to challenges in both analog design and signal integrity. With ever higher speeds, and smaller geometry technology trends, design engineers must continually contend with shrinking signal-to-noise ratios. Transient noise simulations allow them to realistically predict signal and noise combinations and interactions. This is definitely a hot topic of interest for the future!
Input well taken, I have just signed Scott for an other post on HPP transient noise…..
That’s it for this post. If you want more information (and more visual content :)) , you can use the following link to our 2012 HSPICE SIG Videolog page :
A bientot !