Analog Simulation Insights

 

Q&A: Sigrity discusses S-parameter modeling and characterization using HSPICE

So… In our previous blog, we promised you an interview with one of our speakers at DesignCon AMS tutorial (that’s if you manage to read my blog until the end 🙂 ).  Well here we go !

DesignCon AMS tutorial emphasizes on S-parameter modeling and simulation for Signal Integrity Analysis. As a chairman for this track, I contacted three senior SI engineers in this domain:Brad Brim, Sigrity; Amir H. Motamedi, Aruba Networks; Donald Telian, SiGuys.

In this interview, Brad Brim shares his insights about his incoming experience as a speaker for this event and his experience using HSPICE.

Brad Brim has over 20 years experience in electronic design automation. His responsibilities with Sigrity include market and product management for electrical model extraction and system-level simulation across chip, package and board domains. His present areas of focus are signal integrity and power integrity for high-speed designs. His background includes roles in development, applications and marketing for both components and systems from high-speed digital to RF/microwave/antenna.

Q: could you please describe your job responsibilities? What kind of circuits did you simulate using HSPICE and which specific simulator capabilities did you focus on?

My role at Sigrity is “marketing”, but please don’t hold that against me 😉  This includes the familiar responsibilities of product definition and promotion but also includes being a technical expert for internal and external consulting.  The products for which I am directly responsible are in the area of “extraction” and “analysis” for signal integrity (SI) and power integrity (PI) across the physical domains of chip, package and board.  My background includes many years of EM and circuit simulation algorithm development and applications of such to a large breadth of high-frequency and high-speed designs.  My experiences and current responsibilities span design simulation for components, circuits and complete systems.

I apply a number of simulation tools in my daily efforts, including Sigrity extraction tools and Synopsys HSPICE.  The majority of Sigrity tool users are also HSPICE users and the synergies between the two toolsets are of primary importance to our tool users.  Whether S-parameter models extracted by PowerSI, RLGC and IBIS package models from XtractIM or power-aware IBIS 5.0 buffer models converted from transistor netlists by T2B; nearly all model extractions by the tools for which I am responsible are eventually applied in HSPICE. Users of Sigrity tools are typically concerned with whole-board/package designs and combining chip/package/board models for characterization of entire systems. Even our block-level system analysis environment SystemSI applies HSPICE as a circuit simulation engine for characterization of serial channels and parallel buses. We provide technical support on a daily basis to our customers who are applying S-parameters directly in HSPICE, or indirectly applying such through HSPICE-specific macromodels. We have, as have our tool users, noticed a marked improvement in recent releases of HSPICE for efficiency and robustness in dealing with frequency domain model data. This has enabled our tool users to address not just wider parallel bus designs but to also include greater electrical resolution (more nodes) of the power delivery network (PDN) in their system simulations. This is especially important for power-dominated applications such as simultaneous switching output (SSO), where detail of the PDN must be included for proper system-level characterization. Even for characterization of high-speed serial channels the ability to handle high-pin-count S-parameter models enables consideration of PDN effects and their influence on jitter.

Q: Can you tell us more about the section of the tutorial you are covering? What can attendees gain from your presentation ?

My portion of the tutorial is to review the basics of S-parameters. All of what I will address can be found in the literature or college texts. However, there are a number of subtle details we all seem to forget all too-often. These details are often the assumptions upon which further analysis of circuits and systems are based, and as we all know, false assumptions lead to questionable analysis results. For example, it is critically important to recall that S-parameters are a “differential” measurement; a two-terminal concept, just like voltage. You know the difference of voltage between the two terminals, but not the absolute (i.e. global ground referenced) voltage at either of the two terminals. Many EDA tool users, and even some EDA analysis tools, tend to forget this concept and therefore improperly apply S-parameter models. This often results in questioning of the S-parameter models rather than the manner in which they were applied. My goal is to convey an intuitive understanding of these concepts in hopes the attendees will learn how to more effectively and correctly apply S-parameter models for their circuit and system level simulations.

Q: What is your overall impression on using HSPICE for Signal Integrity? What are the key capabilities and where do you think SYNOPSYS should focus on moving forward?

I observe HSPICE to be one the most widely applied EDA tool by Signal Integrity engineers worldwide. A number of other schematic capture environments, layout based SI-only simulations and assorted time-/frequency-domain circuit simulators are commonly applied for boards and packages. But even as a stand-alone circuit simulation engine HSPICE may be the most widely applied tool for SI applications. This is because pre-layout netlist based investigations are supported well with excellent circuit simulation algorithms, transistor-level circuit convergence is good and libraries are available for many of the devices and circuits applied by SI engineers. Then, for verification of system-level behavior HSPICE is again applied to assemble component, circuit and whole-board/package and even chip models to simulation of complete systems. HSPICE has addressed a number of detailed challenges to support this verification flow. One example is direct application of Sigrity’s broadband network parameter (BNP) file format for S-parameter data. This provides HSPICE with the ability to read very compact sized data files while retaining access to full spectral content of the underlying data; simultaneously boosting accuracy and increasing accuracy.

You have certainly received feedback from may HSPICE users for where they wish enhancements. There’s always what I call “great taste, less filling”, which is larger/faster simulations that consume less memory to complete. One area of concern I hear repeatedly from SI engineers, especially those who apply transistor-level buffer models is “convergence”. You’ve made good progress in recent releases with application of frequency-domain data and I assume this effort will continue. In addition HSPICE now supports power-aware IBIS 5.0 buffer models. This is a necessary step to enable full-bus design of memory interfaces and their seemingly now-required SSO analysis with PDN effects. CPU core speeds are not increasing as rapidly as in years past so parallelization or distributed computing may be an avenue to increase both speed and capacity. This can require a lot more work than one may first expect, since basic algorithms and sequential process assumptions applied throughout many years of code development must be reexamined.

Q- What do you foresee for Signal Integrity in the next five years?

I foresee SI/PI engineers addressing larger portions of the system and doing so with more electrical resolution. Switching speeds will continue to increase, driving bandwidths even higher for SI/PI engineers to consider. Wider memory buses will be characterized in-full and the interaction between unique buses will be desired in simulations. The interaction amongst many high-speed serial channels will be required. In a sense, high speed serial and parallel bus design concepts may become more similar than they are today. I foresee a further blending of SI and PI issues and the engineering responsibility for such. It is quickly becoming a requirement to include PDN effects, even for high-speed serial channel design. These practices imply circuit simulations of increasingly larger size and complexity. A larger number of CPU cores will be available for engineering desktop compute environments and EDA tool users will expect full utilization of their compute hardware. Distributed computing environments are becoming more popular in larger corporations and this trend is likely to continue. However, I suspect design data security issues may mitigate short term adoption of cloud computing for EDA applications. All of this implies there are bright employment opportunities for many more SI/PI engineers. Further, both Synopsys and Sigrity have a lot on our plates to address these future needs.

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