Analog Simulation Insights

Archive for 2012

 

MTV 2012 Mixed Signal Verification Panel – Can Mixed Signal verification be done with no analog solver ?

Well, it has been a while, hasn’t it? No, I have not been lazy, I have just been busy working on Synopsys amazing portfolio of simulators. 🙂

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Posted in AMS Assertions, AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, verification | Comments Off on MTV 2012 Mixed Signal Verification Panel – Can Mixed Signal verification be done with no analog solver ?

 

Q&A : How ST optimized their validation flow and decreased turn-around time by 8X using Synopsys Custom Explorer

You may have watched the previous video I posted on CustomExplorer Ultra (if not, it is not too late :)). A very interesting feature of this tool is its Waveform comparison capability.

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Posted in AMS EDA tools, analog, Device Modeling, EDA, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized | Comments Off on Q&A : How ST optimized their validation flow and decreased turn-around time by 8X using Synopsys Custom Explorer

 

Optimizing your Mixed Signal Verification Environment using CustomExplorer Ultra – Part 1

With increasing complexity of mixed-signal designs comes a more and more expensive coverage scheme for verification, from the analog as well as the digital side. Finding a verification cockpit combining ease-of-use, performance and required features for both Analog and Digital is therefore not a trivial task.

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Posted in AMS EDA tools, EDA, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification | Comments Off on Optimizing your Mixed Signal Verification Environment using CustomExplorer Ultra – Part 1

 

Call for papers for IEEE 2013 WMED conference

After three weeks of well-deserved Mediterranean vacations :), I am back on line.  Don’t worry, I am not going to talk about my open-water swim experiences, but about the call for papers for 2013 WMED, which is scheduled to take place on Friday, April 12, 2013 in the Student Union Building of Boise State University. http://www.ewh.ieee.org/r6/boise/wmed2013/WMED2013.html

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Posted in AMS EDA tools, Device Modeling, IEEE Conferences | Comments Off on Call for papers for IEEE 2013 WMED conference

 

Rambus significantly speed up their DFT Logic and Timing Verification in Mixed-Signal Designs using CustomSim-VCS

In our latest blog entries, Synopsys mixed-signal customers talked about their verification flow. Those posts described known aspects of mixed-signal environment (such as for example behavioral modeling). I wanted to highlight today a slightly different usage of Synopsys mixed signal solution among some of our customers. Using performance and ease of use of CustomSim-VCS, DFT verification engineers are able to get a considerable speedup in their simulations.

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Posted in AMS EDA tools, analog, Fast-SPICE, Mixed Signal/Cosimulation, verification | Comments Off on Rambus significantly speed up their DFT Logic and Timing Verification in Mixed-Signal Designs using CustomSim-VCS

 

AMD talks about advanced regression and verification for Mixed-Signal Designs using CustomExplorerUltra

If you read my blog or other EDA related blogs, you probably have already figured out that verification, specifically for mixed-signal designs, is getting increasingly complex. Different variables have to be taken in consideration: complexity of your design environment or topology, high-volume of regression runs, simulation speed are just a few of those . The verification methodology has also to support multiple languages, and work with different netlist formats available across the industry. As such, there is a crucial need for an integrated mixed-signal verification environment that focuses on functionality, reliability, and performance.

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Posted in AMS Circuits, AMS EDA tools, EDA, Fast-SPICE, Mixed Signal/Cosimulation, verification | Comments Off on AMD talks about advanced regression and verification for Mixed-Signal Designs using CustomExplorerUltra

 

Q&A: STE innovates their mixed-signal verification using CustomSim-VCS solution with real number modeling on AMS design

Verification is getting to be a more and more critical step in today IC designs. As more and more analog designs evolve into mixed-signal ones, verification methodologies and strategies need to be further refined and improved to address new challenges. While the verification of the logic part, mostly implemented in Verilog and VHDL, has gained momentum, the analog part suffers from not being supported by this language. To speed up the verification of the analog part (SPICE, Verilog-A(MS), VHDL-AMS), innovation is needed.

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Posted in AMS Assertions, AMS Circuits, AMS EDA tools, analog design, digital, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification | Comments Off on Q&A: STE innovates their mixed-signal verification using CustomSim-VCS solution with real number modeling on AMS design

 

7 Tips to improve your Verilog-AMS model

Well, because this blog is a technical blog, I thought it was a good time for a geek-friendly post :).  Armed with my usual optimism and with the help of our in-house expert Dave Cronauer, I decided to give you a few tips to make your Verilog-AMS module more efficient. Dealing with customer issues for many years, one recurrent observation I had about behavioral models is that performance is strongly correlated with the quality of your module. Using a simpler model and changing some of your modeling techniques can bring you a significant speed up in term of simulations.

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Posted in Behavioral Modeling, Mixed Signal/Cosimulation, Uncategorized | Comments Off on 7 Tips to improve your Verilog-AMS model

 

Call for Abstracts is now open for DesignCon 2013 !

As a chair(wo)man for the AMS track at DesignCon (yes I know, you heard it before 🙂 ), I just want to inform you that the call for abstracts is now open for DesignCon 2013:

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Posted in AMS Circuits, AMS EDA tools, analog, IEEE Conferences, RF, Signal Integrity, Uncategorized, verification | Comments Off on Call for Abstracts is now open for DesignCon 2013 !

 

Q&A with ST-Ericsson: Latest ERC flow innovations using CustomSim CCK for optimal verification coverage

Circuit design implementation has become increasingly complex in deep submicron technologies. Multiple processor cores, I/Os peripherals, complex analog circuits, and logic are now being implemented onto the same chip. Ensuring product reliability to meet design goals and to achieve good yield has become a crucial step in today design cycle. With complex IP, system integration, and multiple power domains, you need an extremely flexible and powerful EDA solution to tackle those circuit verification demands.

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Posted in AMS Circuits, AMS EDA tools, analog design, EDA, Fast-SPICE, Reliability, verification | Comments Off on Q&A with ST-Ericsson: Latest ERC flow innovations using CustomSim CCK for optimal verification coverage