NanoTime is our transistor-level static timing product for custom designs. Since Custom Designer is for custom design too it was natural that we’d integrate the two tools together. Released in June of 2010, the NanoTime integration into Custom Designer lets users do concurrent timing and SI analysis for designs of up to 6 million devices and see the whole timing picture in schematics and layout.
Getting to the end-game faster in a chip design project is one of the driving forces for EDA. As EDA tools have matured over the years parts of the design flow have emerged as a major block of time. In custom design, the layout phase of blocks has become one area that needed serious attention. This phase often occupies as much 60 percent of the overall time for a given block and is an obvious target for productivity enhancers in a custom design tool.
I was recently at an offsite where CAD engineers, Designers, and Custom Designer developers were all present. We were reviewing capabilities and deployments of Custom Designer in our IP business. One of the CAD engineers was reviewing some capabilities they had implemented using Hercules manipulation of GDS that allowed analog designers to better “see” their designs and optimize the layout.
Today’s Guest Blogger is Dwayne Holst, Corporate Applications Engineer for CustomExplorer and Custom WaveView at Synopsys.
High accuracy analog simulations face the classic problem of scalability. Doubling the size of a design roughly quadruples the size of the matrix and dramatically increases a simulation’s run time to the point where a design team simply cannot wait for it to finish. Conversely, the team cannot proceed without knowing that the design is functioning. Conundrum!
For those of you who made it to the recent San Jose SNUG meeting, you may have noticed a presentation titled, “Using Custom Designer to ‘Blow Up’ a Design”. I can assure you there were no pyrotechnics involved – the ‘Blow Up” really meant ‘Scale Up” since the paper detailed how we were able to use the power of Custom Designer to reverse the sands of time. Our normal IP flow is a forward migration from an existing process node down the scaling curve to a more advanced – smaller – node. In this case, several customers requested a 130nm implementation of a piece of our production proven IP that had just been released on 65nm. Our customer made this request for a variety of reasons but one key reason was tied to the higher cost of 65nm mask production. Moving the design to 130nm would save them a ton of money even if it seems to be moving backwards.
I’m new to this blog stuff. I usually spend my days with my head down working through specs, schedules and the accompanying blizzard of emails and phone calls as we work out the details of the next big release. So, again, welcome–and here we go!
Hello, and welcome to our new blog on the state of custom and AMS IC design at Synopsys. We set out some years ago to address the need for alternatives in custom and analog design software, and with the launch of Galaxy Custom Designer in 2008 we are seeing that vision realized.