Analog Simulation Insights

 

AMS Verification at ICCAD

I wasn’t able to attend myself, but there was an interesting session on AMS verification at the most recent ICCAD in San Jose: DESIGNERS’ PANEL: Mixed-signal Simulation Challenges and Solutions. Richard Goering has a report on the panel discussion at SCD Source – Designers cite mixed-signal challenges and solutions.

There are some important lessons to be drawn from the panelist’s presentations in Richard’s report:

1. A hierarchical verification methodology is the only way to go for complex, high-performance mixed-signal SoCs.

The challenges of verifying a 40 Gbit/second CMOS deserializer IC, presented by William Walker of Fujitsu Labs, makes this abundantly clear. While this problem was described as “outside the envelope of what CAD tools are capable of verifying today“, I think it would be more accurate to say there is no SINGLE CAD tool – it takes a hierarchical methodology built from several tools that are best-suited for various aspects of the problem.

Think about this… when you go for your next annual physical checkup, would you want your doctor to use just one instrument to verify your health? That could be painful, not to mention totally ineffective!

The hierarchical methodology described in this example includes:

  • SPICE for highest accuracy at the block level
  • FastSPICE to accelerate verification of difficult multi-rate circuits, such as PLLs
  • Verilog-AMS for chip-level functional verification
  • Matlab Simulink for top level architectural modeling

2. EDA vendors need to focus more attention on flows, not just point tools.

So, even if you agree that a hierarchical methodology is required, you may ask “how do I put one together”? While there are certainly some gaps that still call for better point-tool solutions; such as time-domain noise and jitter analysis, I believe that the bigger issue is that EDA vendors don’t give enough attention to the integration of their tools into seamless verification flows.

Now, to defend EDA vendors somewhat, while this is a big problem for users it is an even bigger problem for tool developers. They just don’t have the knowledge and expertise to take a design through a complete flow. Developing a flow requires a closer working partnership between vendors and customers, and all too often the customer can’t share their most difficult designs outside their company. The result is a lot of reactive bug reports and enhancement requests, rather than proactive joint development.

Another problem is that the best tool for each task may come from a different vendor. This is why it is worrisome to hear that some vendors are pulling back on their interoperability programs. I would like to call for an initiative to create a verification equivalent to the OpenAccess Interoperable PDK Library industry alliance. This is a critical industry need.

3. You can’t just just throw as much data as you can create at a tool and expect it to spit out an answer.

I’m not referring to garbage-in/garbage-out here. This is in some ways even worse, the case of too much data in… and nothing out! I have also seen many examples of “extraction overload”, as was described in the ICCAD discussion by John Croix of Nascentric. This is the challenge of post-layout transistor-level verification. Designers and verification engineers sometimes fear missing some minute detail in the extracted parasitics from their layouts, so you see netlists bogged down by milli-ohm resistors and atto-farad capacitors that have no meaningful effect on circuit performance. Post-layout analysis is a critical part of a hierarchical verification methodology, which requires close integration between extraction tools and simulators. These tools tend to live in separate worlds, both at EDA vendors and with users; the physical/geometric view of the design database and the electrical/schematic view of the circuit that the layout implements. Accurate parasitic reduction is required, along with intelligent back-annotation heuristics. From experience, I suggest looking into tools such as HSIMplus if you are choking simulations with flat, multi-gigabyte parasitic files.

-Mike

p.s. I have been informed that this blog, and the other Synopsys Open Community blogs, will be moving by Dec-6 to a new location on the new Synopsys.com website. The RSS feeds should still work, and the URLs will get forwarded, so you should not lose contact with your subscriptions. A new look & feel should make the entire site easier to use and navigate.

p.p.s. If you have been using Yahoo readers for your blog subscription… well you might not be seeing this at all. Nevertheless, for some reason Yahoo is not refreshing the feeds for Synopsys blogs, so that it appears nothing new has been posted in a long time. I don’t know if the new web site will fix that, but for now I can no longer recommend using Yahoo for blog subscriptions. Please see the new link to subscribe by email through Feed Burner. I know that one still works.




The World is Analog

  • Print
  • Digg
  • del.icio.us
  • Facebook
  • Google Bookmarks
  • LinkedIn
  • RSS
  • Twitter