Analog Simulation Insights


Square pegs and round holes

Hi All,

There was another Accellera discussion this week on the topic of AMS assertions. To be more accurate, the discussion has actually focused more on how to define analog properties in System Verilog. Now this is a great example of the type of “analog meets digital” issue we explore here, but I have to say that I just can’t get this image of square pegs and round holes out of my head on this. You know… you might be able to get them to fit together, but only if you make the peg small enough. And therein lies the issue, at least in regards to sizing a solution to fit a problem… and the problem here is how to improve AMS verification.

If you look at the IEEE 1800TM Standard for SystemVerilog (which you can download from the link if you have an IEEE Xplore® account), you will see that the spec defines seven types of (logical) properties:

  1. sequence
  2. negation (NOT a property)
  3. disjunction (OR of two properties)
  4. conjunction (AND of two properties)
  5. if…else (IF A then property B)
  6. implication (when A then property B)
  7. instantiation (you’ll have to look that one up)

Now it’s no wonder I am an analog guy. Logical combinations (NOT, AND, OR) count as new properties???

In any case, look at my Taxonomy of analog properties and you will see that only categories #4 and #7 are a potential fit with the defined System Verilog digital properties.

  1. Connectivity properties
  2. Static electrical properties
  3. Functional properties
  4. Single-event temporal properties
  5. Cumulative temporal properties
  6. Frequency domain properties
  7. Mixed-signal interface properties

So, how do we fit the round peg into the square hole? Or should we?

I found this statement from the IEEE 1800 spec to be extremely interesting (pg. 244):

One of the goals of SystemVerilog assertions is to provide a common semantic meaning for assertions so that they can be used to drive various design and verification tools.”

The SV assertions are specifically designed to work with digital verification tools; digital simulators, formal verification tools, and coverage measurement tools. Should we not then be looking at how to best define analog assertions so that they work with analog verification tools? Looking at the little piece of analog that fits with a popular digital verification language certainly has its merits, but I also think that it leaves too much out when it comes to meeting the actual objective of improving AMS verification.

If we instead look at the problem from the point-of-view of what analog properties are, as the developers of the IEEE-1800 standard did for digital, we can get a much better solution. And, I think that it’s actually not so hard to do.

Each of the analog/electrical properties in my taxonomy can be verified by tools that are in use today. The definition of an analog property can refer to the type of analysis or tool required, just as the digital assertions do. And… just as the Verilog-AMS LRM does for models, with analysis-dependent functions.

In the end, the SV assertions come down to a simple true/false boolean value. If we let the analog tools do what they do best, i.e. analyze analog properties and set pass/fail flags, it would be much easier than trying to fit that round peg into a square hole. In fact, that is very similar to some experimental work done at IIT Kharagpur on verification of time domain mixed-signal properties. I believe that this concept, of using optimized analog property checkers, linked to SV where it fits, is the way to go for comprehensive “analog meets digital” verification.

I hope to hear more of your thoughts on the subject.


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