Posted by mike demler on August 27, 2008
Oh, wait a second… those are affirmations, and we’re here to talk about assertions. Right… sorry for the confusion. (And Apologies to Al Franken).
So what is an AMS assertion, you may ask? It’s understandable if there is confusion here, especially if you come from the analog part of this blog audience. If you work in the digital verification world, you are probably already very familiar with the concept. In analog, we are still in the definition stage.
The Verification Methodology Manual for SystemVerilog (or VMM) defines an assertion this way:
“Assertions are observers that monitor signals in the DUT for correct behavior.”
Not part of some self-help program after all! That sounds pretty simple, doesn’t it?
>You mean like .MEASURE statements in SPICE?
Yes, I think the .MEASURE would qualify as an analog equivalent of an assertion. But, as with all things analog/mixed-signal the digital world has it much easier. (See … Because digital design is so easy!).
Personally, I would generalize the VMM definition of “assertion” in this context. Here’s my definition:
An assertion is a means to monitor some property of your design that you must verify in order to meet spec.
Now in the digital world it might make sense to use “property” and “signals” interchangeably. In digital – signals and properties can be simply represented by binary value(s), and the properties to be monitored are event-driven; i.e. they can generally be described in reference to a clock, another binary signal, or some prerequisite sequence of logical states. Everything is described in the time domain.
But in analog… signals are not so straightforward! And many of the properties that must be verified are not even signals per se, nor are they necessarily measured in the time domain.
In digital they use languages, like Verilog, to describe the design. So it’s a natural to add some commands for verification to these languages ; hence SystemVerilog assertions, or the PSL Property Specification Language, two of the IEEE standard verification languages. In analog, we don’t do language-based design… which brings us to the issue of the day. The goal of assertions is to automate design verification. We could definitely use more automation in AMS verification, but how would this assertion concept work? What “language” would we use? And what does an AMS property look like anyway?
All these questions are now being discussed in a new working group of Accellera; the standards-making organization that just recently released version 2.3 of Verilog AMS. I am participating in these discussions, and would like to hear from some of you as we work to define these concepts further. I welcome your thoughts or comments here.
In researching the topic of AMS assertions myself, I came across another event to add to our calendar of AMS Verification-related workshops and conference. SASIMI is the “Workshop on Synthesis And System Integration of Mixed Information technologies”. The next occurrence of SASIMI will be March 9-10 , 2009, in Okinawa, Japan. I was particularly interested to find this paper presented at the 2007 SASIMI workshop: “Analog Simulation Meets Digital Verification – A Formal Assertion Approach for Mixed-Signal Verification“. The authors are from the Universities of Frankfurt, Tuebingen, and the Ilmenau Technical University in Germany. You can click on the link above to can find a copy of the paper online. The topic fits very well with the “analog meets digital” theme that we explore here. It is also a very good example of the work that is going in in several places around the world, to advance the state of the art in AMS verification.
I will be exploring the topic of AMS assertions, along with how we can define AMS properties, more in forthcoming blog posts. There are a surprising (to me at least) number of people working in this area, so I am especially interested in hearing from you.