Posted by mike demler on June 30, 2008
Some of you may be familiar with the concept of formal verification for digital circuits. If you look at the Wikipedia definition, you will see that formal verification is a process of “proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics.” Phew!!!
Doesn’t sound like that would work for AMS circuits, does it? Digital designs can apply boolean logic to check that a design is “correct by construction”, but how would that work for analog/mixed-signal?
I just came across a small workshop that is being held in exactly two weeks, which focuses on exactly this topic. Papers are being presented by a small group that is actively working on the development of formal verification for analog. I’m wondering if any of you are familiar with this conference, especially if you have attended or are planning to attend. The workshop is part of the 20th International Conference on Computer Aided Verification, which is also new to me. Since I am an analog guy of course 🙂
A few of the topics to be presented:
The invited talk fits right in here with the topic of how analog meets digital in verification. Unfortunately, I will be on vacation so won’t be able to attend myself. (Hawaii or New Jersey…. hmm…)
If any of you do attend please let me know, since I think that our readers would be very interested in a report.