- I am still hearing lots of positive feedback on the AMS Verification Breakfast that we held on Tuesday. It looks like we hit on the key issue effecting AMS design in this so-called “the Year for Analog”. Attendance at my suite presentation on A Methodology for Mixed-Signal Circuit Design & Verification with Discovery-AMS and Synopsys’ Custom Environment has been very high. Many attendees have said that they wish they could have attended the AMS breakfast, so please check back here to find out when we have the video replay up on the Synopsys website for viewing. It should take us about 30 days after DAC.
- From a customer at one of my suite presentations: “That is exactly the problem that we had at my company”! He was referring to this chart:
The chart shows that the problem of how analog meets digital is the major cause of chip failures as AMS content in SoCs continues to increase. The problem comes from analog and digital living in their own design & verification flows until it comes time to put the silicon together. It’s great to her that we are focusing on the right thing, and not some lesser issues that the non-cognescenti think represent progress in AMS.
Design Automation Conference
AMS verification Verilog-AMS