Analog Simulation Insights


things heard at DAC – Day 1

  • Dan Payne, fellow AMS EDA blogger, stopped by to chat about news regarding HSPICE, HSIM, NanoSim, XA, etc. Interesting question he asked me: “what is the biggest change since last year”? It would have to be the implementation of multi-threading in all of our simulators, to take advantage of the newest multi-core processors.
  • I had a very interactive session with attendees at my 4PM presentation on A Methodology for Mixed-Signal Circuit Design & Verification with Discovery-AMS and Synopsys’ Custom Environment. One of the interesting issues raised… if parasitics are so critical (and they definitely are!) what good does it do to simulate the pre-layout schematic without them? Predicting parasitics is a very tough problem, since post-layout effects create the need for instance-based device models that are specific to placement and proximity to other devices. Have any of you used an internal tool to predict parasitics in your designs? Know of any tools that do this? I know it is an issue that will be brought up at our AMS Verification Breakfast tomorrow as well.
  • Most erroneous statement of the day – from an EDA vendor presentation: “Analog design is stuck at 90nm”! Wow… If you are trying to sell AMS tools to analog designers, you need to really understand where they are at and what their issues are. As I have written before: Reports of the Death of AMS SoCs are Greatly Exaggerated

This statement is out of touch, and was used to promote a solution in search of a problem. Here are just a few examples of AMS designs from ISSCC 2008 that are moving along with Moore’s Law:

  • 90nm – A quad-band single-chip GSM radio with transmitter calibration in 90nm digital CMOS
  • 65nm – A fully digital CMOS transmitter for the 2.4-to-2.7GHz WiFi/WiMax bands using 5.4GHz ΔΣ DACs
  • 45nm – A continuous time ΔΣ ADC for voice coding with 92db DR in 45nm CMOS

That’s all for now.


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