Posted by mike demler on May 28, 2008
No… I’m not referring to the infamous Denali Party at DAC. It’s really hard to be hip if you dress like those guys in Disco Inferno. No, if you really want to get HIP at DAC, you need to know about the HSPICE Integrator Program. Clever… eh? 🙂
I think we all know that SPICE simulation is the #1 day-to-day workhorse tool for circuit designers. You’ve seen me write about this before (Analog design is NOT black magic… but it is VERY hard, and More “black magic” mumbo jumbo… will it ever end?). Nevertheless, there is still a lot of whining in the press (generally not from analog designers) about how SPICE has been in use for so long… so therefore nothing new has been done in analog EDA. To which I say hogwash!. It may be true that SPICE has been around at least as long as disco, but the difference is that SPICE, and particularly HSPICE has never gone out of style.
There is a lot that’s new with HSPICE and Fast-SPICE, which you can hear about in the Synopsys DAC presentation titled “Advances In Circuit Simulation and Mixed-Signal Verification“.
Here is the description:
Come see the latest improvements in Synopsys’ transistor-level circuit simulation solution. This session will cover updates on the latest 40-nm device models, performance improvement and multi-core in HSPICE, fast and accurate transient simulation and mixed-signal verification in FastSPICE, and the best-in-class mixed-signal waveform analysis and debug capabilities.
Other simulators compare themselves to HSPICE because HSPICE is the incumbent gold standard in the industry. HSPICE has the highest level of silicon correlation in the industry, and recently Synopsys partnered with TSMC to develop the modeling interface technology that will be used for 40nm and beyond. An entire network of companies (or ecosystem in marketing speak) provide value-added solutions that employ HSPICE as the core simulation engine. To better support this HSPICE ecosystem, Synopsys recently created the HSPICE Integrator Program. Twenty-five EDA vendors composed the founding group of companies for HIP.
You can hear more about HIP when you visit DAC in Anaheim. You will see HIP members displaying the “integrated with HSPICE” stamp on their presentations.
With silicon-accuracy being such a critical issue, I would like to highlight two of the HIP members that will be showing solutions for more accurately modeling silicon variability. This goes straight to the issue I have discussed recently about how silly it is to focus on matching one SPICE simulation data point, rather than looking at the true distribution of circuit performance (Simulation accuracy… it’s the silicon, ******!).
Solido Design Automation will be presenting a technical seminar at DAC titled “Variation Robustness for Analog/Mixed-Signal, Custom Digital and Memory Design“. New techniques to accelerate, increase accuracy and derive more information from statistical variation analysis will be presented. You can find out more about the Solido solution for performing statistical variation analysis by clicking on the link to register for their seminar.
MunEDA will also be presenting their HIP solution at DAC in an “Automatic Flow for Library Cell Optimization with Synopsys HSPICE® & MunEDA WiCkeD™“. The MunEDA solution enables users to take into account inter- and intra-die variation and the effects on parametric performance such as leakage and timing. As an added incentive there will be a Bavarian Beer event at the MunEDA booth on Wednesday afternoon.
So… it’s too bad there is nothing new going on in analog EDA, huh?
Don’t forget to register for the Synopsys AMS breakfast at the Marriott on Tuesday morning. Our topic is AMS Verification and Moore’s Law… solutions for 45nm and beyond.
I hope to see you in Anaheim.