Posted by mike demler on February 26, 2008
DVCon, which describes itself as “the premier conference for functional design and verification of digital electronic systems“, was held in San Jose on February 19-21. Though the conference emphasizes digital systems, some of the challenges of verifying the increasing amount of mixed-signal content in SOCs were addressed in the Analog/Mixed-Signal Verification session on Thursday morning.
Here are my notes from the first paper, in what turned out to be a very interesting session at DVCon last week. I will follow with my review of the other two papers in that session.
7.1: Functional Verification in the Presence of Linear Analog Circuits
The first presentation was from Thomas J. Sheffler of Rambus, Inc. Thomas’s presentation described a solution for verifying the behavior of analog circuits that are parametrically controlled by digital logic as part of a “big-D/little-a” system. The example used was a PHY output driver that is tuned through programmable current DACs to minimize reflections and interference on a high-speed serial data link. Digital control modulates the voltage value that is transmitted based on the calibrated, weighted sum of the bit stream to reduce inter-symbol interference.
The system verification challenge is to confirm that the proper bit voltage is implemented for a given control word value, and to check for errors such as swapped or inverted control bit logic. In this case the analog values that must be measured are actually piece-wise constant, simplifying the problem by requiring only DC measurements. I am seeing many examples like this however, where the need is for a mechanism to read-back analog values for verification in a digital environment. The 2nd paper in this session also addressed this in a different way.
Functional verification was complicated by the segmented DAC architecture which employed a combination of binary-weighted current sources for the LSBs, along with equally-weighted thermometer-coded current sources for the MSBs. This type of DAC architecture creates the possibility for an incorrect control code to produce the “correct” output voltage, since each of the MSBs has the same weight.
The novel solution offered here was to build a Verilog PLI library of models for linear circuit elements that are parameterized by passing real values (i.e. the analog quantities – resistance, DC current, etc.) during simulation. The Verilog Procedural Interface (VPI) enables C-language function calls to the models, and Verilog register values can then be used to control each parameterized element. By interconnecting instances of the linear model building blocks, the complete functionality of a DAC-controlled PHY can be emulated. A voltage probe is also included in the model library, to read the electrical value of the output result that is to be tested and compare it to the expect value.
This paper reinforces the need for an efficient way to model digitally-controlled analog circuits in D/a designs, so that mixed-signal blocks can be incorporated easily in digital verification methodologies. It was interesting to me that the authors dismissed Verilog-AMS as a solution because of concerns for computational overhead in an analog solver. These are precisely the type of problems that the analog extensions to Verilog were intended to address. In the case of dynamic simulation, it is true that performance can be dominated by the nonlinear differential equations that must be solved for the analog portion of a mixed-signal circuit.
However, by abstracting analog behavior to linear piecewise-constant models the problem is converted to simple DC nodal analysis – and there is no longer any need for solving differential equations. This should eliminate the concern for computational overhead of a SPICE simulator in transient mode. Simple co-simulation through VPI or a commercial AMS simulator that integrates Verilog with a SPICE or Fast-SPICE engine, such as in Synopsys’ Discovery-AMS, would suffice. Co-simulation of SPICE with Verilog functions as an event-driven interface, where the Verilog simulator makes calls to the SPICE solver – just as was done here with a specialized nodal analysis algorithm. It would be interesting to compare performance to see which is faster.
But, perhaps a full-blown SPICE or Fast-SPICE engine would be overkill. Let me ask you, my readers…
Are there many AMS verification problems that would require only a DC SPICE capability to be linked to a Verilog or VHDL simulator?
What are your thoughts?