Posted by mike demler on February 13, 2008
Now how’s that for a subject line? Sounds pretty theoretical doesn’t it?
Well, don’t worry, this is not going to be some academic treatise on numerical methods or matrix algebra. My objective is simply to clear up any confusion that may exist regarding how Fast-SPICE accelerates regular SPICE simulation.
Not all Fast-SPICE simulators are hierarchical. As far as I know, hierarchical simulation was an innovation that was introduced by Nassda in what is now Synopsys’ HSIM (HS = hierarchical storage). The illustration below shows how it works. Hierarchical storage just takes advantage of the fact that most circuits are hierarchical, consisting of multiple instances of subcircuits, so that memory storage can be reduced by only storing a subcircuit once. This does not affect accuracy at all, but it does speedup up simulation by creating a smaller image of the circuit in memory. Obviously, memory circuits can take the greatest advantage of this, but circuit designers know that subcircuit reuse and hierarchy is by no means unique to memory designs. Similarly, Fast-SPICE simulators that exploit this technique are not just for memories, as one of the speakers at the recent DesignCon claimed. Exploiting hierarchy is one of those obvious things that, once you see it, you wonder why all simulators don’t work that way. Much more efficient!
Hierarchical storage is sometimes confused with the other Fast-SPICE innovation introduced by HSIM, the IM=isomorphic matching. Isomorphism refers to the identification of structurally and ELECTRICALLY identical structures during simulation. This technique is used during simulation, whereas hierarchy is used during the initial netlist read-in.
When a simulator like HSIM uses isomorphism, identical instances throughout the hierarchy are evaluated to determine if their port currents and voltages match to within a (user-controllable) tolerance. If they don’t match, each instance is solved individually. If they do match, then why waste the time? This could result in a speed-accuracy tradeoff if the tolerances are too large, or the isomorphism is only transient, but it can dramatically speed up many simulations with no significant loss of accuracy as well.
In post-layout designers quite often have one big flat netlist, and one might think that this means that hierarchical Fast-SPICE no longer applies. Not true! It is very rare that every transistor or subcircuit instance is entirely unique, even after parasitic extraction and back-annotation. A simulator like HSIM, along with the HSIMplus post-layout technology, is capable of re-constructing hierarchy even from a flat parasitic extraction and back-annotation in order to maintain the performance benefits of hierarchy and isomorphic matching. This provides a unique double benefit, where Fast-SPICE may be both FASTER and MORE ACCURATE than SPICE. (Another truism that belies the myth of “analog Fast-SPICE“).
With Hierarchical Back-Annotation, it is possible to simulate a circuit that was just too large or too slow to even think about simulating in a conventional SPICE simulator that lacks hierarchy and isomorphism. As a result, a designer would have to compromise with only a pre-layout simulation or by piecing together a set of smaller simulations, hoping that the results were accurate. Hierarchical Fast-SPICE can handle the post-layout parasitics much better, and as a result more accurate and faster post-layout verification can be achieved.