Analog Simulation Insights


Reports of the Death of AMS SoCs are Greatly Exaggerated

Happy New Year Everyone!

In a recent EETimes article (“Shift in the integration equation”) Bill Schweber predicted that a revival of hybrid, multi-chip packaging techniques will soon take the place of continuing higher levels of integration in AMS SoCs. I’m having some serious déjà vu after reading that one! I know it was a long holiday break, but it is 2007… ooops… 2008….. right??I can’t recall how long ago it was that I first heard such an argument, but it must have been at least 20 years ago.

Once upon a time MCMs (multi-chip modules) were going to take over, then there was System-in-Package (SiP), and now we are reading about Chip-Scale Packaging (CSP). It all amounts to the same issue that designers faced decades ago – how to best partition a design to achieve the required cost/power/performance objectives.Analog designers are generally very risk-averse, so the challenge of designing circuits in ever-shrinking processes with ever-lower voltages is enough to bring back nostalgic memories of selecting a specialized process to work in… to get away from those tiny little noisy, leaky, low-voltage digital transistors. While there are a small number of cases where SiP can be a viable choice, there is no going ‘back to the future’ that never was. With consumer electronics as the major driver of the semiconductor industry cost, power, and portability dictate that AMS SoCs are here to stay and the levels of functionality and performance being achieved show no signs of abating.Nowadays there is an explosion beyond AMS to AMS/RF, that was thought to be impossible just a few years ago… especially in CMOS.

If you need proof, then I suggest you check out the program for the upcoming International Solid-State Circuits Conference (ISSCC), which will be held in San Francisco on February 3-7. For more than 50 years ISSCC has been the premier showcase for the world of analog, transistor-level design.This year is no different, and it will be exciting to see the abundance of RF-AMS designs that will be presented in 90nm, 65nm, and even down to 45nm CMOS and beyond. I did see one SiP paper in the ISSCC program, but here are some selected highlights that overwhelmingly demonstrates that, despite reports to the contrary, there is absolutely no slowing down on the roadmap to ever-higher levels of AMS and RF integration:

On Monday, February 4th:

In Session 3 on Filters and Amplifiers

·Paper 3.1: NEC presents “A Widely-Tunable Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio”, fabricated in 90nm CMOS.

In Session 5 on High-Speed Transceivers

·Paper 5.1: Hitachi presents “An 8Gb/s Transceiver with a 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for a -36.8dB-loss Backplane”; a 90nm CMOS 8Gb/s transceiver.

·Paper 5.7: IBM presents “A T-Coil-Enhanced 8.5Gb/s High-Swing Source-Series-Terminated Transmitter in 65nm Bulk CMOS

In Session 6 on UWB Potpourri

·Paper 6.7: NXP presents “A 0.6-to-10GHz Receiver Front-End in 45nm CMOS

·Paper 6.8: Georgia Institute of Technology presents “A 90nm CMOS 60GHz Radio”. A 60GHz transmitter and a 60GHz receiver are integrated in standard 90nm CMOS.

On Tuesday morning, February 5th:

In Session 9 on MM-Wave & Phased Arrays

·Paper 9.1: University of Toronto and ST Microelectronics present “A 95GHz Receiver with Fundamental-Frequency VCO and Static Frequency Divider in 65nm Digital CMOS”; a fully integrated receiver spanning the 76-to-95GHz band is designed in 65nm digital CMOS.

In Session 10 on Cellular Transceivers

·Paper 10.5: Texas Instruments presents “A 24mm2 Quad-Band Single-Chip GSM Radio in 90nm Digital CMOS

·Paper 10.7: Broadcom presents “A Low-Power WCDMA Transmitter with an Integrated Notch Filter”. A filtering technique to attenuate the receive-band noise enables a 65nm CMOS WCDMA transmitter to achieve an output noise level of -160dBc/Hz at 80MHz offset, while dissipating 65mW.

In Session 11 on Optical Communication

·Paper 11.7: ClariPhy Communications presents “A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion Compensation of Multi-mode Optical Fibers at 10Gb/s”. A 6b 10GS/s ADC feeds a parallel processing DSP receiver.

In Session 12 on High-Efficiency Data Converters

·Paper 12.1: IMEC and University of Salento present “An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS”.

·Paper 12.7: ST Microelectronics presents “A 1.2V 4.5mW 10b 100MS/s Pipelined ADC in 65nm CMOS”.

Tuesday afternoon, February 5th:

In Session 17 on Wideband Receivers

·Paper 17.1: University of Twente presents “A Discrete-Time Mixing Receiver Architecture in 65nm CMOS with Wideband Harmonic Rejection”.

In Session 20 on WLAN/WPAN

·Paper 20.1: Intel presents “A 1×2 MIMO Multi-Band CMOS Transceiver with an Integrated Front-End in 90nm CMOS for 802.11a/g/n WLAN Applications”.

·Paper 20.3: ST Microelectronics presents “A Fully-Digital 65nm CMOS Transmitter for the 2.4-to-2.7GHz WiFi/WiMAX Bands using 5.4GHz ΔΣ RF DACs”.

On Wednesday morning, February 6th:

In Session 25 on Building Blocks For High-Speed Transceivers

  • Paper 25.2: Conexant Systems presents “An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL”, in 90nm-CMOS.

In Session 26 on Wireless Frequency Generation

  • Paper 26.1: University of Florida presents “A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna”. A 410GHz push–push oscillator with an on-chip patch antenna is fabricated using low leakage transistors of a 6M 45nm CMOS process.

In Session 27 on ΔΣ Data Converters

  • Paper 27.7: University of California and Conexant Systems present, “A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection”.
  • Paper 27.8: Infineon presents “A CT ΔΣ ADC for Voice Coding with 92dB DR in 45nm CMOS”.

In Session 29 on Trends In Communication Circuits & Systems

  • Paper 29.4: IMEC presents, “Advanced Planar Bulk and Multigate CMOS technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies”. The effect on analog/RF circuits of different options for CMOS downscaling beyond 45nm is investigated. Measurements on comparators, opamps and VCOs show high speed potential for planar bulk CMOS with strain, and superior low-frequency analog performance for FinFETs.

On Wednesday afternoon, February 6th:

In Session 30 on Data Converter Techniques

  • Paper 30.4: MediaTek presents “A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS”.

In Session 31 on RF & MM-Wave Power Amplifiers

  • Paper 31.3: Fujitsu Laboratories presents “60 and 77GHz Power Amplifiers in Standard 90nm CMOS”.
  • Paper 31.5: University of Washington and Intel present “A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation”.

So, it’s not hard to see that any reports of the death of AMS SoCs are highly exaggerated.

Happy New Year! Have a Great ’08.

Hope to see you at ISSCC.


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