More comments on AMS Verification at ICCAD: modeling parasitic effects
In his comments on AMS Verification at ICCAD, responding to my remarks on the challenge of post-layout transistor-level verification, Martin asked:
Posted in analog
Followup to comments on AMS Verification at ICCAD: languages & tools
Hello Everyone,
Posted in analog
AMS Verification at ICCAD
I wasn’t able to attend myself, but there was an interesting session on AMS verification at the most recent ICCAD in San Jose: DESIGNERS’ PANEL: Mixed-signal Simulation Challenges and Solutions. Richard Goering has a report on the panel discussion at SCD Source – Designers cite mixed-signal challenges and solutions.
Posted in analog
Follow up to comments
This is a follow up to comments on my post AMS assertions… a violation of “the 10 commandments”?
Posted in AMS EDA tools, analog, analog design, SPICE
AMS assertions… a violation of “the 10 commandments”?
Now… before any religious zealots come after me, “the 10 commandments” that I refer to are in my friend Karen Bartleson’s list of Commandments for Effective Standards. If you have been reading here in recent months, you know that I have been participating in Accellera discussions on the topic of AMS assertions. After the last two meetings, I have grown more concerned that this activity is committing transgressions of Karen’s 3.1th commandment: “Know when to start“. I might modify that slightly to say “know WHERE to start“.
Posted in analog
Accellera Discussions on AMS Assertions
The Verilog-AMS Technical Subcommittee of Accellera held another in a series of conference call discussions on Tuesday Oct-7, to further explore the topic of AMS Assertions. The meeting began with a review of some work that was published at the workshop on Formal Verification of Analog Circuits, which I wrote about here in June.
Posted in AMS Assertions
