Analog Simulation Insights


Red Herrings: separating the truth from the hype in SPICE verification tools

From Merriam-Webster:

red herring: something that distracts attention from the real issue.

There’s been an awful lot of hype published recently on the topic of SPICE tools for analog/mixed-signal verification. As a long-time AMS designer myself, my nose is keenly sensitive to the smell of a red herring; i.e. marketing hype disguised as the solution to a real technical issue. For me, this is especially true when the topic regards the tools of analog design.

Lately I have seen two new breeds of red herring being tossed around, and they have even been given names; “analog fastSPICE” and “digital fastSPICE”. Must be Mr. Red Herring and Mrs. Red Herring… or something like that. Meet the Herrings… isn’t that a new Ben Stiller movie?

Uh oh, I better check… which one do I have? I sure don’t want to be using the wrong one!

This attempt at labeling just reminds me of all the 0 trans fat packaging I see in the grocery stores these days. Ooooh… zero trans fat!! Whoopee!! I’m on my way to a healthy lifestyle now! NOT!

So, let’s address what some marketing campaigns have been calling digital Fast-SPICE. The latest description I read claims that so-called digital Fast-SPICE is a type of simulator that has these characteristics:

  • Don’t generate or maintain a DC operating point
  • Utilize simplified device models
  • Partition into sub-circuits and independently solving the matrix for each
  • Use event-driven simulation
  • Require block-level simulator tuning
  • Utilize hierarchy to represent “redundant” circuitry

It’s true, all of these techniques have been used, some of them in decades past, to speed up transistor-level simulation. Is each and every one of these techniques used in the leading Fast-SPICE simulators today? No, they are not!

You must read the fine print carefully because the truth is in the details, and you don’t get to the facts unless you are willing to read past the hyped-up label. What’s patently not true here is the claim that the use of these techniques necessarily compromises accuracy to such a degree that a new and improved, 0 trans fat version of Fast-SPICE is required for verification of your analog circuit. That is just a big red herring.

In my experience the real issues that designers have with simulators are performance, accuracy, and capacity, followed by ease-of-use. The so-called analog Fast-SPICE tools are claiming true SPICE accuracy 5x-10x faster. Well, first-of-all… can anybody tell me what is TRUE SPICE accuracy? I hate to break it to you, but the real deal ain’t SPICE.. it’s the silicon. Nevertheless, let’s go with that for a minute.

If there is such a thing as TRUE SPICE, for more than 25 years that has been HSPICE. Now, you can check my bio… I work for the company that sells HSPICE, so accuse me of bias if you like. But I used HSPICE way back in 1981, when my personal well being was on the line for getting 1st silicon to work. So, I know very well of what I write. These are the facts; HSPICE is still the 1st SPICE simulator that the foundries use for development of new models, calibrated to the latest silicon. It has been that way going back to the days of the level-28 model. So how can any analog Fast-SPICE simulator provide TRUE SPICE accuracy, if it doesn’t share the same device models with HSPICE?

But back to the real issues; performance, accuracy and capacity. Is 5-10X fast enough? Many times it is not. Let’s look at some of those allegedly digital Fast-SPICE techniques. Let’s take partitioning as an example. If you have a critical analog block that is part of a large, mixed-signal SoC, doesn’t it make sense to apply a higher level of accuracy where it is needed, and get better performance where it is not? Breaking down the problem into constituent parts… that’s what engineers do! What’s the alternative? Should designers waste cycles in an analog Fast-SPICE simulator that can’t partition, and can’t simulate non-critical portions of a circuit efficiently? Doesn’t make any sense to me.

Now let’s look at hierarchy, and the ability to exploit redundancy. (That’s generally referred to as isomorphic matching). DOH!!! Is this a bad thing? If you had 10 identical circuit blocks, that were used identically and saw identical loads and stimulus at a given point in time, would you want to waste simulation time repeating the exact same calculations to simulate those blocks 10 times? Engineers are nothing if not compulsively efficient, and that also makes absolutely no sense.

Think about it. Back in college when you were studying circuit analysis, learning all about Kirchoff’s laws and such… did you ever feel the need to solve the same test question 10 times during your final exams? I certainly hope not! Designers may be obsessive at times, but that would just be sick.

I’ll finish with one more supposedly digital technique: block-level simulator tuning. Now, the ironic thing is that that is EXACTLY what an analog Fast-SPICE tool is. It’s tuned for small analog blocks! It doesn’t handle the largest circuits, because it can’t exploit redundancy. If you have digital blocks… forget it! It can’t run fast enough for the largest mixed-signal devices, because it doesn’t do partitioning.

Analog designers know that there is never a free lunch. Trade-offs are what analog designers do for a living. It’s not a matter of analog Fast-SPICE versus digital Fast-SPICE. The real issue is having a tool that can provide the best performance, accuracy, capacity and ease-of-use. Some tools are adept at giving the user the flexibility to make the choice on what is most important. Designers are knowledgeable enough to choose based on the facts. Caveat emptor… let the buyer beware. Don’t be fooled by red herrings and misleading labels.


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