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SAE is Free!

Posted by Hélène Thibiéroz on February 3rd, 2016

Hello everyone,

I have some exciting news to share with you! You might have seen the announcement today that we are including a native Simulation and Analysis Environment (SAE) with our HSPICE, FineSim, CustomSim and VCS AMS circuit simulators. If you have not already seen the news article, here is the link:

http://news.synopsys.com/2016-02-03-Synopsys-Redefines-Circuit-Simulation-with-Native-Environment

Included at no extra cost in the upcoming 2016.03 release of these simulators, SAE eliminates the need for bolt-on third-party environments for Synopsys circuit simulation customers.

What is SAE?

SAE is a comprehensive transistor-level simulation and analysis environment that is tightly integrated and included with Synopsys’ circuit simulators to improve analog verification productivity. The netlist-based flow of SAE provides intuitive and comprehensive capabilities to efficiently set up and launch simulations, and analyze and explore simulation results to improve the productivity of analog verification.

illo_sample_file

What are the key capabilities and benefits of SAE?

  • Included with CustomSim, FineSim, HSPICE, and VCS AMS at no cost
  • Eliminates the need for integrating Synopsys simulators into third-party analog design environments
  • GUI access to all advanced features available in Synopsys SPICE and FastSPICE simulators
  • Unique netlist-based flow for direct import of SPICE, Verilog and DSPF
  • Comprehensive simulation management utilities such as multi-testbench setup, sweeps and corners, and remote grid job distribution
  • Integrated with Custom WaveView graphical waveform viewer for extensive post-processing
  • Advanced visual data navigation and data mining features, such as statistical and multi-parameter charts

Picture1

We will premiere a one-hour webinar “Improving Analog Verification Productivity Using Synopsys’ Simulation and Analysis Environment (SAE)” on Wednesday, February 17, 2016 at 10:00 a.m. PST. This webinar provides an introduction to SAE and its key capabilities for improving productivity and throughput, and will be available for on-demand viewing for the remainder of 2016.

To learn more about SAE, please visit the SAE page on the Synopsys web site.

If you have specific questions, please contact Deepa Kannan, Technical Marketing Manager for SAE at deepa.kannan@synopsys.com.

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Posted in AMS Circuits, analog, analog design, Fast-SPICE, HSPICE, SPICE, verification | No Comments »

Is Your MOSFET Suffering the Effects of Aging?

Posted by Hélène Thibiéroz on January 29th, 2016

Hello everyone,

We have more new tidbits for our Synopsys HSPICE users!

Due to popular demand, we posted a new HSPICE Tips & Tricks webisode – #7 in the series – on MOS Reliability and Analysis (MOSRA) Level 3. In this 15-minute webisode, Synopsys Sr. R&D Manager Joddy Wang explains the formulation of HSPICE’s built-in MOSRA Level 3 model that accurately captures two major aging effects in MOSFETs: the Hot Carrier Injection (HCI) effect and the Bias Temperature Instability (BTI) effect. In this webisode, you will learn what measurement data is needed to extract and validate a MOSRA Level 3 model.

To help you become familiar with MOSRA, the complete demo case used in this webisode is available for free – watch the webisode to request your own copy and try it out!

WT11739_HSPICE_TipsAndTricks_Webisode7_MicroSite_SL1

We continue to add to the HSPICE Tips & Tricks Webisode Series, a collection of mini webinars to help make your simulation tasks easier and more productive. Topics that have been covered so far include: S-element, eye diagrams, IBIS-AMI, RUNLVL, and Monte Carlo analysis. Look for the next webisode on MOSRA Aging Simulation and Analysis of CMOS Circuits to premiere in February.

Is there a topic you’d like us to address in an upcoming webisode? Feel free to let us know by adding a comment on the web page.

Hope the beginning of 2016 has been very good for all of you!

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Posted in analog, analog design, Device Modeling, digital, Fast-SPICE, HSPICE, Nanometer CMOS, Reliability, SPICE, verification | No Comments »

Don’t Miss the HSPICE SIG Dinner in Santa Clara!

Posted by Hélène Thibiéroz on January 14th, 2016

Happy Thursday!

I just wanted to remind our Synopsys HSPICE users (and other AMS aficionados…) about our annual HSPICE SIG event that is coming up next Wednesday during DesignCon. This live event offers attendees an opportunity to visit HSPICE Integrator Program (HIP) partner exhibits during the cocktail hour, then listen to technical presentations during dinner on topics related to circuit simulation challenges.

This year, engineers from Altera, Cisco, Qualcomm, Xilinx will speak on a variety of interesting topics, including creating non-linear models, using transient analysis, StatEye, and Synopsys’ environment for SPICE simulation and analysis. Scott Wedge, our popular “HSPICE guy” will address “HSPICE 2016 FAQs and Figures”.

DATE: January 20, 2016

TIME: 6:00 p.m.-9:00 p.m.

LOCATION: Santa Clara Marriott Hotel
2700 Mission College Boulevard
Santa Clara, CA 95054

To register for the event, visit the HSPICE SIG web page at: http://www.synopsys.com/Tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/hspice-sig2016.aspx

We look forward to seeing you there!

WT11551_HSPICE_SIG16_MicroSite_SL1

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Posted in AMS Circuits, AMS EDA tools, analog design, HSPICE, Power integrity, Signal Integrity, SPICE | No Comments »

Synopsys new blog “Custom Layout Insights” is here !

Posted by Hélène Thibiéroz on January 7th, 2016

Happy new year/ Bonne annee to everyone,

You may have seen in my recent posts customer interviews on how they are successfully using Synopsys simulation and analysis environment for their advanced process nodes design. This is only one part of Synopsys’ unified solution for custom and cell-based design and verification. I wanted therefore to introduce Synopsys new blog “Custom Layout Insights” hosted and written by Graham Etchells.

Graham Etchell

Graham Etchell

Graham has been involved with EDA since the late 1970’s and has over 35 years’ experience with custom layout tools. Because of his expertise, I will strongly encourage you to take a look at his blog where over the coming months he will enlighten you on what we at Synopsys are doing in the custom layout space. And believe me, there is a lot going on ! :)

To access his blog, you can use the following link:

https://blogs.synopsys.com/customlayoutinsights/

Enjoy the blog !

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Q&A with Altera: How to improve your advanced-node design productivity using Synopsys SPICE Simulation and Analysis environment

Posted by Hélène Thibiéroz on December 15th, 2015

Greetings,

You may have noticed from my previous post that we had a very successful event in Austin. I therefore wanted to share with you some of the technical content.  One of the aspects we cover is the increasing amount of analysis and debugging that needs to be done as design companies are moving to advanced process nodes.  While SPICE simulators keep improving performance and algorithms to allow designers to run more simulations faster, designers are left with an increasing large amount of data they need to be able to analyze and debug quickly.  Synopsys SPICE simulation environment provides a standalone solution to quickly simulate, analyze and debug advanced design nodes design to improve your productivity and reduce your design cycle.

Sireesha Dhulipati presented their usage for advanced node designs and how they are currently leveraging SAE to automate the analysis process and significantly increase their design productivity.

Sireesha Dhulipati works as an advanced CAD engineer at Altera working in the circuit simulation CAD team. She has received her master in electrical engineering from San Jose state University.

Blog_Sireesha

  •  What are Altera needs in term of analog mixed-signal verification? Which specific challenges are you faced with in term of analyzing and debugging more and more complex designs?

High-speed memory makes design very challenging due to signal integrity, skew, and noise management issues. These high speed memory devices require very tight timing margin requirements between the data and clock. These tight timing requirements and very stringent board requirements introduce several design challenges. With the increase in the edge rates of I/Os associated with a memory interface, the design of the link between the input buffer and the output buffer is becoming very challenging.  Faster edges of the signals are very sensitive to any discontinuities on the transmission path.  Signal integrity issues such as reflections/ringing due to high input capacitance and noise due to power/ground oscillations are becoming more pronounced, requiring a thorough evaluation.

In addition, when moving to advanced node technologies, we are facing with more and  more challenges in running and analyzing transistor-level designs  as we have multiple test benches with multiple formats with different simulation setups and tightening constraints to meet our yield requirements which requires more MC simulations to be run and analyzed.

Data post processing is also a challenge as we analyze tons of data. We also do a lot of mixed signal verification and we need an environment for easier processing, viewing and probing of both analog and digital results

For these reasons, using the advanced GUI SAE becomes a crucial need for delivering high quality designs in time with a low TTM.

  • What motivated Altera to start using SAE? Which specific technical features and flows were especially useful in reducing analysis time?  

SAE is an advanced user interface which supports versatile simulation setup, custom scripting capabilities and also post processing features for complex debugging which increases productivity.

Some of the specific technical features would include

•             MC simulations with multiple PVT corners and sweeping across some of the design variables.

•             Multiple test bench support and parasitic simulations

•             Mixed signal simulations

•             Post processing capabilities – data mining, charts cross probing, report generation

 

  • Can you talk more about the type of verification you did?

At Altera we do multi-dimensional verification – our designs are so complex that we can’t anymore use simple corners. We have to use complex corners configurations with multiple global corners, corner groups and sweeping across multiple test-benches that require a more advanced GUI to also enable all the post processing features. SAE enables these features to do our multi-dimensional verification.

Some of the types of designs we used are various blocks in PLL, CDR in the transmitter and receiver sections. Since these are highly sensitive analog blocks, we do run a lot of Monte Carlo simulations with local and global variations we also need to run advanced noise analysis for Jitter and eye diagram plotting.  Some of the post layout designs would have a size of around 500k MOSFET’s in them to evaluate which needs a good GUI to probe different parts of the design after simulations and analysis on them.

  • What was your overall assessment of SAE and the main differentiating points versus other tools?

While evaluating SAE, we used 20 test benches on 13 circuits selected with the following characteristics

  • Circuits: PLLs, bandgaps, clock networks, loop filters, M20K, charge pump, serializer, etc.
  • Processes: 20nm and 14nm
  • Analysis: DC, AC, transient, and Monte Carlo
  • Measurements: Delay, voltage, current, gain, bandwidth, mean, and standard deviation
  • Pre and post-layout designs

Features that were compared with the other GUI’s– post processing capabilities, mixed signal verification, advanced noise analysis and post layout simulations setup, huge Monte Carlo data handling and graphic way of displaying with Worst-case corner analysis, possible ways of improving the yield of the circuit.

After testing those circuits with complex corner definitions and tons of Monte Carlo analysis with multiple sweeps that generate a lot of data to post process, we found that SAE stand out as a leader versus other commercial GUI’s by providing advanced capabilities (such as data mining, scatterplot capabilities,…) to quickly and efficiently simulate and analyze very large amount of data.

Thank you Sireesha, it was a pleasure to have you as a speaker at our Austin AMS SIG event.

If you are interested in hearing more about Synopsys SAE capabilities, please contact me or your Synopsys account person anytime.

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Great success for Synopsys Austin AMS SIG event

Posted by Hélène Thibiéroz on November 24th, 2015

Happy pre-Turkey D-2 day !

For the poor folks like me still working or the ones surfing the web for Thanksgiving new recipes, I decided to give you, not my grandmother award winning recipe for french gravy, but a technical summary for our first Synopsys Austin AMS SIG event.

We had a very successful event during ICCAD where more than 120 persons came to learn about the latest technical features offered by Synopsys AMS tools. We started from SoC level with mixed-signal verification to end with device modeling and more specifically FinFET modeling.

Bramha Marathe

 Our first speaker was Bramha Marathe, from Qualcomm. Technologies Inc. He is currently director of engineering, Central Verification & Validation Team at  Qualcomm Technologies Inc . He gave to the audience a great presentation on how his design teams extended digital verification to analog  using VCS AMS. His first key point was a seamless migration to AMS verification by being able to minimally change testbench and by taking  advantage of VCS AMS superior performance features (save and restore for example) for regression. His second topic was the capability to  adopt the best of digital verification methodology for mixed-signal (assertions, functional coverage) that are being offered by AMS testbench  technology. His last key point was the capability to extend low power verification to AMS (by using VCS AMS UPF extension and power  calculation checks ).

Mandeep Singh

Our second speaker was Mandeep Singh, custom circuit CAD manager at Samsung Austin R&D center. He demonstrated how memory simulation challenges increase when moving to advanced technology nodes and more specifically FinFET designs. Factors such as increasing extracted netlist complexity, larger number of signoff corners going from 32nm to 10nm drastically impact fast turn-around time at low accuracy cost to ensure time to market. Mandeep demonstrated how his team was able to leverage FineSim SPICE continuous performance improvements from 32nm to 14nm  to keep this TTM constant while moving to advanced process nodes.

Sireesha Dhulipati

Our third speaker was Sireesha Dhulipati from Altera Corporation. While the two first speakers highlighted Synopsys simulators technical features and performance improvments, Sireesha demonstrated how Altera successfully used Synopsys SPICE simulation environment (SAE) to drastically improve advanced-node design productivity. They tested several features (advanced test-bench support, large scale multi-dimensions verification, statistical analysis and data mining, WaveView capability for more advanced measurement definition) on various circuits (SerDes, PLL’s, clock networks, filters with pre and post layout simulations for large scale verification and memory designs for efficient visualization of yield and data correlation) and presented the successful results of their evaluations.

Blog_Joddy

Our last speaker closed our event with the foundation of AMS simulation, device modeling, and more specifically FinFET modeling. Joddy Wang, senior R&D manager at Synopsys responsible for the device modeling team,  covered in detailed FinFET device modeling challenges and Synopsys solution, optimized for both performance and accuracy.

So overall great success and great technical presentations, feel free to contact me anytime if you have any questions.

With that,  I wish to all you a very Happy Thanksgiving.

Speaker LinkedIn profiles:

Brahma Maranthe

Mandeep Singh

Sireesha Dhulipati

Joddy Wang

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Join us for our first AMS SIG event in Austin during ICCAD

Posted by Hélène Thibiéroz on October 29th, 2015

Hello all,

Just a short note to make you aware of our first AMS SIG event in Austin! What is SIG?  Our AMS SIG is a a Special Interest Group for Synopsys AMS products. It is a great opportunity to learn about industry challenges, solutions and best practices during our dinner presentations  as well as to network with industry experts and Synopsys R&D during our cocktail hour.

For our first year, we decided to associate our event with ICCAD as it represents a great venue to showcase the  technical content of our customer presentations  and their depth of expertise.

The theme of this event is “Addressing Advanced Simulation Challenges from Pure Analog to SoC and IoT Designs” and we will cover areas from advanced mixed-signal verification to the challenges and latest advancements in FinFET modeling.

all_screens

Our event occurs during ICCAD conference on
Wednesday, November 4, 2015
Doubletree Austin Hotel
Phoenix Central Ballroom
5:30 p.m. – 8:00 p.m.

To register, please use the following link:

https://www.synopsys.com/Tools/Verification/AMSVerification/Pages/ams-sig-iccad.aspx

http://iccad.com/event_details?id=196-117-

Hope to see you there for our cocktail and dinner !!

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DAC 2015 Circuit Simulation Videolog now available

Posted by Hélène Thibiéroz on August 6th, 2015

Greetings,

From my previous post (dated in June, I know, my blogging frequency could be higher:)), you may have noticed that we focus this year’s event to be performance, highlighting through customer presentations how Synopsys circuit simulation tools’ superior performance address mixed-signal design challenges of today and tomorrow.

We had a very successful event with a large audience and speakers from TSMC, Altera, Xilinx and ST.

Well, it is your lucky day, the videolog is now available :)

You can preview our videolog at:

http://www.synopsys.com/Tools/Verification/AMSVerification/Pages/dac-2015-ams-verification-luncheon.aspx

In summary, our panelists gave very strong endorsements, highlighting the superior performance and multi-core scalability of our circuit simulation tools.

DAC_1

Below are the highlights of the talks:

TSMC speaker highlighted how SRAM designs at 16nm/10nm FinFET nodes require simulations on multiple process corners, have tighter accuracy requirements with significantly more RC parasitics. With latest enhancements in CustomSim, TSMC speaker described how they are able to meet the performance and accuracy requirement while maintaining their aggressive timelines.

Altera speaker shared how, through extensive benchmarking, they selected FineSim SPICE over competition due to its single-core performance and multi-core scalability. The speaker shared benchmark data showing FineSim SPICE was on average 2X faster than competition, and endorsed FineSim SPICE as the key ingredient in meeting project schedules for advanced node designs.

Xilinx speaker described how VCS AMS enables them to extend UVM-based digital verification and Real Number models to mixed-signal verification with CustomSim & VCS co-Simulation flow. The speaker endorsed VCS AMS as the fastest mixed-signal simulation solution on the market with better accuracy and easier setup/debug flow.

ST Micro speaker’s talk was focused on how they use CustomSim and VCS AMS for their Smart Power AMS verification for BCD process technology. Key takeaways were that CustomSim and VCS AMS are ST’s reference FastSPICE and mixed-signal simulation solution with superior performance. The speaker endorsed the new BCD optimizations in CustomSim and showed 2X faster results using the latest release of CustomSim.

Great event ! Thanks to our speakers and hope to see you next year. Feel free to contact me anytime if you have any questions.

DAC AMS Panelists

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DAC 2015 Synopsys Circuit Simulation Luncheon: Altera, ST, TSMC and Xilinx on Synopsys Industry Leading Performance for Analog Mixed-signal Designs

Posted by Hélène Thibiéroz on May 27th, 2015

Improving the performance of existing technologies has always been a key element in the development of computational systems and EDA tools. However, as analog mixed-signal designs complexity drastically increases, conventional techniques are becoming outdated and new technologies must be adopted by designers.

As such, we wanted the focus of this year’s event to be performance, highlighting through customer presentations how Synopsys circuit simulation tools’ superior performance allows analog/mixed-signal circuit designers to address the challenges of today and tomorrow.

During this lunch event, Altera, STMicrolectronics, TSMC and Xilinx will present their experiences using leading performance techniques recently implemented in Synopsys’ AMS simulators. These experts will share their successes in boosting performance and bringing their methodologies to the next level from SRAM to Memory and FPGA for advanced process nodes.

DAC Synopsys AMS Luncheon

This event will be held  on Monday, June 8, 2015 from 11:30 a.m to 1:30 p.m. at the Park Central Hotel (formerly Westin), Metropolitan Ballroom III.

Attendance at this event is free, but registration is required. And in addition to a delectable lunch, attendees will be entered into a drawing to win a GoPro HERO4 Silver camera :)

You can learn more about this event and register at:

http://www.synopsys.com/Tools/Verification/AMSVerification/Pages/dac-2015-ams-verification-luncheon.aspx

As far as  performance in the context of advanced nodes layout and design, you also may want to attend Synopsys Custom Design Luncheon, where key customers would present how adopting Synopsys Custom Design Tools enabled them to speed advanced-node layout .

For more information and to register, you can use the link below:

http://www.synopsys.com/Tools/Implementation/CustomImplementation/Pages/dac-2015-custom-design-luncheon.aspx

Looking forward to seeing you there !

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Posted in AMS EDA tools, EDA, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, verification | No Comments »

VCS AMS at DVCON : Xilinx talk, demos, technical sessions and much more :)

Posted by Hélène Thibiéroz on February 27th, 2015

Happy Friday,

DVCON 2015 is just around the corner so I wanted to inform you on several events we are having there to showcase VCS AMS:

  • VCS AMS at Synopsys booth #101  :

We will demo VCS AMS in areas appealing to digital verification engineers: Easy transition from digital to mixed-signal, increased performance using Save and Restore, AMS testbench or how to extend UVM to analog, UPF extended to analog and Debugging AMS using Verdi

 VCSAMS

  • Synopsys luncheon: Prashanth Gurunath from Xilinx will talk about VCS AMS usage in his presentation  “Addressing Unique Verification Challenges of Mixed-signal with VCS AMS”
  • We will have a specific mixed-signal technical Session on UPF: Mixed-Signal Verification of UPF Based Designs; Andrew S. Milne, Damian Roberts – Synopsys, Inc.

You can find more information at the following link:

http://www.synopsys.com/Tools/Verification/Pages/dvcon-2015.aspx

Looking forward to seeing you there !

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Posted in Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification | No Comments »