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Analog Insights: Analog/Mixed-Signal Design and Verification Blog
|Analog Insights: Analog/Mixed-Signal Design and Verification Blog|
Welcome to Analog Insights! Our goal is to have an innovative, informative and interactive blog about AMS, from purely analog to mixed signal and RF. AMS is a challenging and fast paced place, so let’s have fun with it and mix it up! I hope you enjoy this blog.
Interestingly, I have been wanting to be an engineer since a very young age. After getting a degree in Doctoral studies in EE, I worked at Motorola, within their advanced process and research center as a Device and Spice characterization engineer for 5 years. I then moved to the EDA industry and have been happily working there for 12 years in the AMS domain. I have multiple technical publications under my belt and am currently the chair(wo)man for DesignCon Analog and Mixed Signal track. Why AMS? Because AMS is a fascinating environment with multiples aspects and challenges that evolve extremely quickly, where you keep redefining solutions and pushing the limits. Now about me, I could say I am French, that I like wine and eat cheese but that would be a little cliché, wouldn’t it? Let’s just say that I am active, that I like to be challenged in life and in sports and that I have a passion for swimming.
Posted by Hélène Thibiéroz on November 24th, 2015
Happy pre-Turkey D-2 day !
For the poor folks like me still working or the ones surfing the web for Thanksgiving new recipes, I decided to give you, not my grandmother award winning recipe for french gravy, but a technical summary for our first Synopsys Austin AMS SIG event.
We had a very successful event during ICCAD where more than 120 persons came to learn about the latest technical features offered by Synopsys AMS tools. We started from SoC level with mixed-signal verification to end with device modeling and more specifically FinFET modeling.
Our first speaker was Bramha Marathe, from Qualcomm. Technologies Inc. He is currently director of engineering, Central Verification & Validation Team at Qualcomm Technologies Inc . He gave to the audience a great presentation on how his design teams extended digital verification to analog using VCS AMS. His first key point was a seamless migration to AMS verification by being able to minimally change testbench and by taking advantage of VCS AMS superior performance features (save and restore for example) for regression. His second topic was the capability to adopt the best of digital verification methodology for mixed-signal (assertions, functioaln coverage) that are being offered by AMS testbench technology. His last key point was the capability to extend low power verification to AMS (by using VCS AMS UPF extension and power calculation checks ).
Our second speaker was Mandeep Singh, custom circuit CAD manager at Samsung Austin R&D center. He demonstrated how memory simulation challenges increase when moving to advanced technology nodes and more specifically FinFET designs. Factors such as increasing extracted netlist complexity, larger number of signoff corners going from 32nm to 10nm drastically impact fast turn-around time at low accuracy cost to ensure time to market. Mandeep demonstrated how his team was able to leverage FineSim SPICE continuous performance improvements from 32nm to 14nm to keep this TTM constant while moving to advanced process nodes.
Our third speaker was Sireesha Dhulipati from Altera Corporation. While the two first speakers highlighted Synopsys simulators technical features and performance improvments, Sireesha demonstrated how Altera successfully used Synopsys SPICE simulation environment (SAE) to drastically improve advanced-node design productivity. They tested several features (advanced test-bench support, large scale multi-dimensions verification, statistical analysis and data mining, WaveView capability for more advanced measurement definition) on various circuits (SerDes, PLL’s, clock networks, filters with pre and post layout simulations for large scale verification and memory designs for efficient visualization of yield and data correlation) and presented the successful results of their evaluations.
Our last speaker closed our event with the foundation of AMS simulation, device modeling, and more specifically FinFET modeling. Joddy Wang, senior R&D manager at Synopsys responsible for the device modeling team, covered in detailes FinFET device modeling challenges and Synopsys solution, optimized for both performance and accuracy.
So overall great success and great technical presentations, feel free to contact me anytime if you have any questions.
With that, I wish to all you a very Happy Thanksgiving.
Speaker LinkedIn profiles:
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Posted by Hélène Thibiéroz on October 29th, 2015
Just a short note to make you aware of our first AMS SIG event in Austin! What is SIG? Our AMS SIG is a a Special Interest Group for Synopsys AMS products. It is a great opportunity to learn about industry challenges, solutions and best practices during our dinner presentations as well as to network with industry experts and Synopsys R&D during our cocktail hour.
For our first year, we decided to associate our event with ICCAD as it represents a great venue to showcase the technical content of our customer presentations and their depth of expertise.
The theme of this event is “Addressing Advanced Simulation Challenges from Pure Analog to SoC and IoT Designs” and we will cover areas from advanced mixed-signal verification to the challenges and latest advancements in FinFET modeling.
Our event occurs during ICCAD conference on
Wednesday, November 4, 2015
Doubletree Austin Hotel
Phoenix Central Ballroom
5:30 p.m. – 8:00 p.m.
To register, please use the following link:
Hope to see you there for our cocktail and dinner !!
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Posted by Hélène Thibiéroz on August 6th, 2015
From my previous post (dated in June, I know, my blogging frequency could be higher:)), you may have noticed that we focus this year’s event to be performance, highlighting through customer presentations how Synopsys circuit simulation tools’ superior performance address mixed-signal design challenges of today and tomorrow.
We had a very successful event with a large audience and speakers from TSMC, Altera, Xilinx and ST.
Well, it is your lucky day, the videolog is now available
You can preview our videolog at:
In summary, our panelists gave very strong endorsements, highlighting the superior performance and multi-core scalability of our circuit simulation tools.
Below are the highlights of the talks:
TSMC speaker highlighted how SRAM designs at 16nm/10nm FinFET nodes require simulations on multiple process corners, have tighter accuracy requirements with significantly more RC parasitics. With latest enhancements in CustomSim, TSMC speaker described how they are able to meet the performance and accuracy requirement while maintaining their aggressive timelines.
Altera speaker shared how, through extensive benchmarking, they selected FineSim SPICE over competition due to its single-core performance and multi-core scalability. The speaker shared benchmark data showing FineSim SPICE was on average 2X faster than competition, and endorsed FineSim SPICE as the key ingredient in meeting project schedules for advanced node designs.
Xilinx speaker described how VCS AMS enables them to extend UVM-based digital verification and Real Number models to mixed-signal verification with CustomSim & VCS co-Simulation flow. The speaker endorsed VCS AMS as the fastest mixed-signal simulation solution on the market with better accuracy and easier setup/debug flow.
ST Micro speaker’s talk was focused on how they use CustomSim and VCS AMS for their Smart Power AMS verification for BCD process technology. Key takeaways were that CustomSim and VCS AMS are ST’s reference FastSPICE and mixed-signal simulation solution with superior performance. The speaker endorsed the new BCD optimizations in CustomSim and showed 2X faster results using the latest release of CustomSim.
Great event ! Thanks to our speakers and hope to see you next year. Feel free to contact me anytime if you have any questions.
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Posted by Hélène Thibiéroz on May 27th, 2015
Improving the performance of existing technologies has always been a key element in the development of computational systems and EDA tools. However, as analog mixed-signal designs complexity drastically increases, conventional techniques are becoming outdated and new technologies must be adopted by designers.
As such, we wanted the focus of this year’s event to be performance, highlighting through customer presentations how Synopsys circuit simulation tools’ superior performance allows analog/mixed-signal circuit designers to address the challenges of today and tomorrow.
During this lunch event, Altera, STMicrolectronics, TSMC and Xilinx will present their experiences using leading performance techniques recently implemented in Synopsys’ AMS simulators. These experts will share their successes in boosting performance and bringing their methodologies to the next level from SRAM to Memory and FPGA for advanced process nodes.
This event will be held on Monday, June 8, 2015 from 11:30 a.m to 1:30 p.m. at the Park Central Hotel (formerly Westin), Metropolitan Ballroom III.
Attendance at this event is free, but registration is required. And in addition to a delectable lunch, attendees will be entered into a drawing to win a GoPro HERO4 Silver camera
You can learn more about this event and register at:
As far as performance in the context of advanced nodes layout and design, you also may want to attend Synopsys Custom Design Luncheon, where key customers would present how adopting Synopsys Custom Design Tools enabled them to speed advanced-node layout .
For more information and to register, you can use the link below:
Looking forward to seeing you there !
Posted in AMS EDA tools, EDA, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, verification | No Comments »
Posted by Hélène Thibiéroz on February 27th, 2015
DVCON 2015 is just around the corner so I wanted to inform you on several events we are having there to showcase VCS AMS:
- VCS AMS at Synopsys booth #101 :
We will demo VCS AMS in areas appealing to digital verification engineers: Easy transition from digital to mixed-signal, increased performance using Save and Restore, AMS testbench or how to extend UVM to analog, UPF extended to analog and Debugging AMS using Verdi
- Synopsys luncheon: Prashanth Gurunath from Xilinx will talk about VCS AMS usage in his presentation “Addressing Unique Verification Challenges of Mixed-signal with VCS AMS”
- We will have a specific mixed-signal technical Session on UPF: Mixed-Signal Verification of UPF Based Designs; Andrew S. Milne, Damian Roberts – Synopsys, Inc.
You can find more information at the following link:
Looking forward to seeing you there !
Posted in Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification | No Comments »
Posted by Hélène Thibiéroz on January 15th, 2015
I just wanted to remind our dear Synopsys HSPICE users (and other AMS aficionados..) about our yearly HSPICE SIG event. This event has grown other the years and present each year topics related to circuit simulation challenges. Because HSPICE combines transistor-level accuracy with comprehensive signal integrity analysis, and is the golden reference for IBI and IBIS-AMI modeling, the SIG presentations this year will focus on signal and power integrity analysis of multi-gigabit serial links.
DATE: January 28, 2015
TIME: 6:00 p.m.-9:00 p.m.
LOCATION: Santa Clara Marriott Hotel
2700 Mission College Boulevard
Santa Clara, CA 95054
To register to our event, you can use the link listed below:
In addition to providing a great dinner and technical presentations by industry leaders and Synopsys R&D, we will also host a cocktail hour where our HSPICE Integrator Program partners will exhibit their circuit simulation solutions.
We are looking forward to meeting you there.
Posted in AMS Circuits, AMS EDA tools, analog design, Signal Integrity | No Comments »
Posted by Hélène Thibiéroz on January 13th, 2015
Happy new year everyone,
The Synopsys AMS Special Interest Group (SIG) is an active community for all Synopsys analog/mixed-signal users and design engineers who want to stay connected with the latest developments in the field of analog/mixed-signal circuit simulation, cell characterization, and custom design.
We are hosting again our AMS SIG event in Bangalore, India on January 21, 2015 at the Park Plaza Hotel . At this event, Analog Devices, ARM, STMicroelectronics and Xilinx panelists will share their insights about using Synopsys’ AMS verification solution for some of today’s most challenging designs, ranging from mixed-signal verification for various design architectures to complex reliability challenges for full-custom IP. The panelists will also discuss future verification needs, as well as the methodology and tool requirements to support modern AMS verification. In addition, Synopsys will present the latest challenges in AMS verification and innovations and new technology features to address those challenges. Lunch will follow to allow attendees to network with our panelists.
To register to this unique event, please go to:
I hope you would appreciate our event, as our goal was to focus on getting some of our most advanced customers present their analog mixed-signal challenges and solutions.
As usual, your comments are more than welcome
Posted in AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized, verification | No Comments »
Posted by Hélène Thibiéroz on October 8th, 2014
VCS AMS is doing really well. After a successful webinar with ST and ARM and the release of a white paper, we are continuing our momentum with a tutorial at DVCON Europe on Tuesday, October 14th:
This highly technical tutorial will presents how the VCS AMS mixed-signal verification solution provides superior performance and flexibility. It was developed around best-in-class methodologies to extend proven digital verification techniques into mixed-signal designs. VCS AMS encompasses, but is not restricted to, capabilities for time efficient simulations using “Save and Restore” technology, aligned with the SV1800 industry standard syntax for “SystemVerilog nettype” constructs, represented as a holistic methodology within AMS Testbench that is underpinned by extremely successful UVM library.
The breadth and depth of usage of the individual portions within the solution are explained by real user case studies: extensive usage of VCS AMS Save and Restore for boosting productivity by STMicroelectronics and performance-driven VCS AMS behavioral modeling flow by Micronas.
So yes, you will miss Octoberfest but you get to attend an amazing webinar
In addition, if you want to access our previous webinar and review VCS AMS white paper “Extending Digital Verification Techniques for Mixed-Signal SoCs with VCS AMS”, I have listed the links below.
VCS AMS webinar
VCS AMS white paper
As usual, your feedback is more than welcome.
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Posted by Hélène Thibiéroz on September 2nd, 2014
I hope you all had a relaxing labor day weekend. To start fall successfully :), we are releasing a joint webinar on VCS AMS with STMicroelectronics and ARM as guest speakers on Wednesday, September 3rd, at 10am PST.
You can register using the following link:
This webinar includes:
- An introduction to the VCS AMS mixed-signal verification solution and key capabilities for coverage-driven AMS testbench development, low-power mixed-signal verification, and regression throughput
- Highlights of how STMicroelectronics is successfully using VCS AMS for both verifying mixed-signal designs using techniques such as assertions and scoreboarding as well as accelerating regression test throughput with the Save and Restore capability
- A description of how ARM is able to use the advanced verification techniques and productivity features of VCS AMS for its validation methodology of physical IP (I/O interface).
This webinar is part of a series on VCS AMS, you can access previous webinars using the following links:
Hope to see you there!
Posted in AMS Assertions, AMS EDA tools, Fast-SPICE, Mixed Signal/Cosimulation, Uncategorized, verification | No Comments »
Posted by Hélène Thibiéroz on July 11th, 2014
We hosted a few weeks ago at DAC Synopsys AMS luncheon with speakers from Micronas, Infineon, AMD and ST. The theme of this year’s event was “Complex Mixed-Signal SoCs: How to Conquer the Next Verification Frontier”.
Our panelists shared their experiences and insights using VCS AMS, our mixed-signal verification solution that incorporates VCS functional verification and CustomSim™ FastSPICE simulator.
We had a packed room and heard many positive comments from the attendees.
Now, if you did not get a chance to attend this amazing event , the videos of all above presentations are now available at the following link:
Below are the titles of the presentations and highlights of the event:
Micronas speaker highlighted how they use mixed-signal verification to ensure “Zero PPM quality” for their customers in automotive applications. They emphasized the need for high performance simulation with SPICE-level accuracy and touted VCS AMS using a reusable testbench strategy for multiple behavioral vs. SPICE netlist configurations as a key methodology for ensuring first-pass silicon success.
Infineon shared the verification challenges they have faced for ARM-based SoCs targeted at a broad array of applications including Automotive, Security, and Energy. They highlighted how the high performance and flexibility of VCS AMS coupled with post-layout support for parasitic/timing back-annotation with CustomSim have helped them to verify the power-up sequence in their complex mixed-signal designs and prevent possible design failures.
AMD described how they have deployed a reusable UVM testbench environment for mixed-signal verification of their complex SerDes PHYs. The speaker shared their successful delivery of IP designs for 28nm and 20nm technologies using VCS AMS, including multicore CustomSim FastSPICE engine, in their regression farm.
ST highlighted how they drive the verification of their Analog/Mixed-Signal systems using VCS AMS and a digital testbench. They showed a detailed comparison of VCS AMS versus competition and emphasized VCS AMS as including the “best FastSPICE engine” and offering the best “Speed and Accuracy” for mixed-signal verification.
So as you can see, a very succesful event so we hope to see you next year !
As usual, any comments or suggestions are more than welcome. Feel free to contact me anytime.
Posted in AMS Circuits, AMS EDA tools, analog, Fast-SPICE, Mixed Signal/Cosimulation, SPICE, Uncategorized, verification | No Comments »
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