Posted by Cary Chin on October 20, 2011
This blog originally posted on the Low Power Engineering Community 8/11/11.
With the current popularity of all things extreme, from extreme dieting, extreme couponing and extreme hoarding, all the way to extreme sports and even extreme programming, I thought, “Why not Extreme Power Efficiency?” After all, power efficiency has been improving at a blistering pace for the last few years. Where will the hotspots and power bottlenecks be looking into the future?
Well, let’s start by rounding up the usual suspects. Dynamic and static power are the buckets into which we partition the energy that is used for computing (flipping bits), vs. the energy used to maintain power to the circuitry (sometimes also called standby power). For dynamic power, much of the focus today is on the back-end of the implementation flow—making sure that capacitances are minimized, dealing with many voltage areas or “islands,” and allowing dynamic variation of voltages and clock frequencies to conserve power. These problems aren’t completely solved today, and continue to expand as power architecture complexity increases, but they are reasonably well understood, with lots of people working on improvements in tools and methodologies. “Extreme” dynamic power efficiency might instead be measured in units of “transitions per function” to gauge the transition-efficiency of any implementation, combined with “joules per transition” for the physical layout and technology efficiency, to arrive at energy consumption estimates. As with any process, you can’t improve what you can’t measure, so thinking about measurements and metrics isn’t a bad place to start.
For static power, we are now pretty good at power gating or “shutdown” to minimize leakage power in unused blocks, and new technology improvements have at least postponed the dreaded explosion in leakage at smaller geometries. However, these problems won’t go away, so as we move forward, “extreme” thinking dictates that power gating will continue to become finer-grained—and to a certain extent the current move toward “3D” transistors is a move in this direction—with much better on-off characteristics such as faster performance and lower leakage. So as the technology enables new transistor designs that approach the “perfect switch,” the tradeoff between finer-grained power-gating vs. more efficient technologies continues to shift.
Finally, while it seems there’s an endless list of things that we need to (and can) worry about, remember that part of what we do everyday is to make practical decisions about priorities. Power efficiency is no different. Worrying about power consumption for one transistor may not seem like much, but multiply it by 3 billion transistors on a chip and suddenly you’re talking real power. At a macro level, an average no-load power (that means no phone on the other end) of 0.1W (0.5W just 3 years ago!) for a cell phone charger isn’t much, but multiplied by the 5 billion mobile phones in the world and 24/7, and you can see we’ve got a big problem. Extreme thinking doesn’t always point us to practical problems that need addressing immediately, but it does allow us to step “outside the box” for a bit just to see what might be out there.