A global team of protocol experts that share their insights and technical expertise in the areas of AMBA, DDR, Ethernet, LPDDR, MIPI, PCIe, SAS, SATA, USB and UFS. This comprehensive team participates in standards committees and will provide the latest information and updates as it relates to your future design considerations.
Featuring speakers from Altera, AMD, ARM, Cavium and Freescale
During DAC 2015, Synopsys hosted a luncheon event at DAC in San Francisco, CA.
Michael Sanie, senior director of verification marketing at Synopsys kicked things off by highlighting the Synopsys Verification Continuum and several key next-generation technologies that are in production and address the need to “Shift-Left” for faster time-to-market. These technologies include Verification Compiler, a broad Verification IP portfolio, the industry’s fastest emulation system ZeBu Server-3, and Verdi, the industry’s de facto SoC debug environment.
Later, a panel of SoC industry experts from Altera, AMD, ARM, Cavium and Freescale shared viewpoints on managing the growing verification complexity and how their leading SoC design teams have achieved success by collaborating with Synopsys.
Carlos Velasco, senior manager, SoC Design Verification Group at Altera described the challenges of verifying and debugging their SoC FPGA. He described their system verification environment, the need for verifying their configuration architecture and SoC Topology, and how Synopsys’ native SystemVerilog technology with full UVM support along with a full range of Verification IP has served them well.
Alex Starr, fellow & pre-silicon solutions architect at AMD painted a picture about rethinking the cost of verifcation. He talked about verification complexity; the importance of methodology; and how emulation with ZeBu and Verdi facilitate hardware-software debug.
Alan Hunter, senior principal design engineer at ARM described the shift-left they have been able to achieve for over 17 years working closely with Synopsys. He described statistical methods, IP-focused system verification, debug and low power verification technologies.
Jim Ellis, director of engineering at Cavium described how they have been addressing the unique verification challenges presented by their ThunderX ARM Processors. He talked about how they were able to shift-left with virtualization, IP and VIP reuse, standardizing their verification flow with VCS, UVM and incorporating Cerititude and VC Formal into their flow.
Robert Oshana, director of software R&D, Digital Networking at Freescale talked about how reference software has been growing a lot faster than Moore’s Law prediction, and how emulating with ZeBu has supported them in their hardware-software debug flow.
Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans.
It is estimated that every smartphone now uses some aspect of the MIPI standards. Last year, one billion phones, and about 6 to 7 billion phone ICs, included a MIPI interface of some sort. MIPI interfaces, especially for cameras and displays, have spread beyond the mobile world into other markets, such as automotive, industrial, medical, the IoT and the digital home/office.
MIPI interfaces make it easier to design complex smartphone SoCs. However, verifying that they are working correctly provides little differentiating value for the end product. The challenge for design and verification teams, therefore, is to implement robust verification environments for MIPI-based designs as efficiently as possible. Developing in-house verification IP (VIP) and test-benches can be costly and time-consuming, especially if they are to exercise the complex traffic patterns, corner cases, errors and exceptions of the more advanced MIPI interfaces. This strategy also puts the verification team at risk of false or missed failures, from poorly implemented or maintained VIP, and may limit VIP reusability from the block to the SoC level.
It may be better to acquire MIPI VIP and testbenches from a commercial provider that can offer a common look, feel, and use model for all VIP and test-benches and so reduce the time it takes the verification team to learn their use. Users of such VIP should also benefit from the fact the VIP has been tried out in multiple contexts and so will model the MIPI protocols, corner cases and error states comprehensively. Commercial VIP is also likely to have been optimized for performance on multiple simulators, and may be delivered with various debug aids.
Since MIPI interface standards are hierarchical, with the more complex interfaces using aspects of the simpler interfaces, MIPI VIP and verification testbenches tend to have a number of common features:
A requirement to both drive the device under test (DUT) and capture its output
The ability to drive the VIP or the DUT from the application side, in cases in which the VIP is acting as a transmitter to the DUT
Reusable data-integrity scoreboarding, so that data-streams can be compared before and after the interface under test
Access to the programming registers of the DUT through a configurable interface
Configurability and customization capabilities
Reusability of the entire verification environment
General Schematic of MIPI Compliance Test Suite
You can learn more about how these common elements recur throughout a suite of MIPI VIP and test-benches, and the way in which more complex MIPI protocols build on lower-level blocks in this article.
There are a lot of common factors in these approaches to verifying MIPI interfaces. IP blocks need to be exercised with a robust set of protocol checks, corner cases, error injection and functional-coverage models to ensure that they comply with the protocols. The VIP and related testbenches need to be kept up-to-date with rapidly evolving specifications and bug fixes. And the verification needs to be rigorous, especially for lower-level blocks such as the PHYs, because more complex interfaces such as UFS rely on them.
Synopsys offers a comprehensive portfolio of VIP for MIPI interfaces, and application using MIPI interfaces, which meets these criteria and offers a common user experience. The portfolio supports the latest versions of the MIPI specifications, and offers comprehensive test suites with functional coverage models, with protocol-aware debug to reduce debug turnaround time. Finally, the VIP blocks are written in SystemVerilog for use on a wide range of simulators.
Synopsys Memory Verification IP is modeled natively in SystemVerilog and supports the common verification standard UVM. Our models support 100% of the memory standard as specified by JEDEC.
Now you can take a deep dive into our VIP solutions at no cost with a hands-on workshop. The workshop will highlight and demonstrate how you can achieve rapid verification convergence on your JEDEC DDR based designs. Through a combination of lecture and lab, we’ll show you how to achieve success in verifying complex SoC designs that include advanced memory protocols such as DDR4/3, LPDDR4/3, UFS, eMMC, HBM, HMC and more.
You and your colleagues can register now for a workshop near you:
Please contact us by email at email@example.com to request a hands-on workshop in your area. Attendance at this event is free, and registration is required. Seating is limited and not all registrations will be accepted. All events are subject to cancellation. For more details, see Memory VIP Workshops.
For more information on MIPI Soundwire, you can download our whitepaper
Major PC audio and mobile companies have been concerned about the limitations of audio interfaces such as PDM, I2S, I2C, SLIMBus and HDAudio for some time. In 2012, the MIPI Alliance LML working group started working on standardization of the Soundwire Interface. In February 2015, the MIPI board adopted version 1.0 of Soundwire Specification. It has the following benefits over other interface technologies:
1. Soundwire supports double data-rate scheme, which reduces power consumption by 40%.
2. Clock-stop mode is provided to save power during idle periods.
3. Frame rate is adjustable to optimize bandwidth and reduce overhead.
4. It has embedded control and command which eliminates the need of other interfaces such as I2C or SPI.
5. The synchronization process uses dynamic sync pattern, which makes synchronization more robust against false synchronization.
6. The transfer protocol is unified for PCM, PDM and general non-audio data.
7. Commands and data are interleaved which reduces latency and it is good for PDM data.
8. It provides bulk transfer protocol for quick startup of devices with DSP capabilities.
9. It implementation is efficient: a simple slave can be as small as 4k gates.
In the next blog, we will discuss a typical use case of Soundwire interface, and how you can leverage Synopsys VIP for MIPI Soundwire to create a test scenario to quickly validate your Soundwire DUT.
For more information on MIPI Soundwire, you can download our whitepaper.