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Virtual Sequences in UVM: Why, How?

Posted by VIP Experts on March 31st, 2015

In my previous blog post, I discussed guidelines to create reusable sequences. Continuing on this thread, here I am going to talk about virtual sequences and the virtual sequencer. Common questions I hear from users include: why do we need a virtual sequence? How can we use it effectively?

Here’s where you can find more information on our Verification IP

Most UVM testbenches are composed of reusable verification components unless we are working on block-level verification of a simple protocol like MIPI-CSI. Consider a scenario of verifying a simple protocol; In this case, we can live with just one sequencer sending the stimulus to the driver. The top-level test will use this sequencer to process the sequences (as described in the previous blog post). Here we may not need a virtual sequence (or a virtual sequencer).

But when we are trying to integrate this IP into our SOC (or top-level block), we surely want to consider reusing out testbench components, which have been used to verify these blocks. Let us consider a simple case where we are integrating two such blocks: two sequencers driving these two blocks. From top-level test, we will need a way to control these two sequencers.

This can be achieved by using a virtual sequencer and virtual sequences. Other way of doing it is to call sequence’s start method explicitly from the top-level test by passing the sequencer to the start method.

I am going to explain this usage by taking an example, where USB host is integrated in an AXI environment. Let’s see how we can control USB sequencer and AXI sequencer from top-level test. For this particular test, I want to configure the AXI registers and then send USB transfers. For configuring AXI registers am using a sequence say axi_cfg_reg_sequence and for sending USB transfers am using the sequence (usb_complex_sequence) which I have used in the previous blog post. Below is an example where multiple sequencers are controlled without using a virtual sequence.

//Top-level test where multiple sequencers are controlled from the
//phase method.
class axi_cfg_usb_bulk_test extends uvm_test;
  `uvm_component_utils(usb_ltssm_bulk_test)

  //Sequences which needs to be exercised
  usb_reset_sequence u_reset_seq;
  axi_reset_sequence a_reset_seq;
  usb_complex_sequence u_bulk_seq;
  axi_cfg_reg_sequence a_cfg_reg_seq;

  function new (strint name=”axi_cfg_usb_bulk_test”,
                uvm_component parent=null);
    …
  endfunction: new

  //Call the reset sequences in the reset_phase
  virtual task reset_phase (uvm_phase phase);
    phase.raise_objections(this);
    …
    //Executing sequences by calling the start method directly by passing the
    //corresponding sequencer
    a_reset_seq.start(env.axi_master_agent_obj.sequencer);
    u_reset_seq.start(env.usb_host_agent_obj.sequencer);
    …
    phase.drop_objections(this);
  endtask:reset_phase

  virtual task main_phase (uvm_phase phase);
    phase.raise_objections(this);
    …
    //Executing sequences by calling the start method directly by passing the
    //corresponding sequencer
    a_cfg_reg_seq.start(env.axi_master_agent_obj.sequencer);
    u_bulk_seq.start(env.usb_host_agent_obj.sequencer);
    …
    phase.drop_objections(this);
  endtask:main_phase
endclass: axi_cfg_usb_bulk_test

This is not the most efficient way of controlling the sequencers as we are directly using the simple sequences inside the test and making it complex. By doing this, we cannot reuse these complex scenarios further to develop more complex scenarios. Rather if we try to create a sequence and use this sequence in the test, then we can re-use these sequences in other tests (or sequences) as well. Also it will be easier to maintain and debug these sequences compared to creating entire scenario in the top-level test.

Having understood why we need virtual sequence and virtual sequencer, let’s see how this can be achieved by taking the same example shown above.

First thing we need to do is to create a virtual sequencer. Note that virtual sequences can only associate with virtual sequencer (but not with non-virtual sequencer). Virtual sequencer is also derived from uvm_sequencer like any other non-virtual sequencer but is not attached to any driver. Virtual sequencer has references to the sequencers we are trying to control. These references are assigned from top environment to the non-virtual sequencers.

//Virtual sequencer having references to non-virtual sequencers
Class system_virtual_sequencer extends uvm_sequencer;
  //References to non-virtual sequencer
  usb_sequencer usb_seqr;
  axi_sequencer axi_seqr;

  function new (string name=”usb_ltssm_bulk_test”,
                uvm_component parent=null);
    …
  endfunction: new

  `uvm_component_utils(system_virtual_sequencer)

endclass: system_virtual_sequencer

//Top level environment, where virtual sequencer’s references
//are connected to non-virtual sequencers
class system_env extends uvm_env;
  //Agents where the non-virtual sequencers are present
  usb_host_agent usb_host_agent_obj;
  axi_master_agent axi_master_agent_obj;
  //Virtual sequencer
  system_virtual_sequencer sys_vir_seqr;

  `uvm_component_utils(system_env)

  function new (string name=”system_env”, uvm_component parent=null);
   …
  endfunction: new

  function void connect_phase(uvm_phase phase);
    //Assigning the virtual sequencer’s references to non-virtual sequencers
    sys_vir_seqr.usb_seqr = usb_host_agent_obj.sequencer;
    sys_vir_seqr.axi_seqr = axi_master_agent_obj.sequencer;
  endfunction: connect_phase

endclass: system_virtual_sequencer

Now we have virtual sequencer with the references to our non-virtual sequencers, which we want to control, let’s see how we can control these non-virtual sequencers using virtual sequences.

Virtual sequences are same as any other sequence but it is associated to a virtual sequencer unlike non-virtual sequences, hence it needs to indicate which non- virtual sequencer it has to use to execute the underlying sequence. Also note that virtual sequence can only execute sequences or other virtual sequences but not the items. Use `uvm_do_on/`uvm_do_on_with to execute non-virtual sequences and `uvm_do/`uvm_do_with to execute other virtual sequences.

//virtual sequence for reset operation
class axi_usb_reset_virtual_sequence extends uvm_sequence;

  `uvm_object_utils(axi_usb_reset_virtual_sequence)

  //non-virtual reset sequences
  usb_reset_sequence u_reset_seq;
  axi_reset_sequence a_reset_seq;

  function new (string name=” axi_usb_reset_virtual_sequence”,
                uvm_component parent=null);
    …
  endfunction: new

  …

  task body();
    …
    //executingnon-virtual sequence on the corresponding
    //non-virtual sequencer using `uvm_do_on
    `uvm_do_on(a_reset_seq, p_sequencer.axi_seqr)
    a_reset_seq.get_response();
    `uvm_do_on(u_reset_seq, p_sequencer.usb_seqr)
    u_reset_seq.get_response();
  endtask: body

endclass: axi_usb_reset_virtual_sequence

//virtual sequence for doing axi register configuration
//followed by USB transfer
class axi_cfg_usb_bulk_virtual_sequence extends uvm_sequence;

  `uvm_object_utils(axi_cfg_usb_bulk_virtual_sequence)
  `uvm_declare_p_sequencer(system_virtual_sequencer)

  //Re-using the non-virtual sequences
  usb_complex_sequence u_bulk_seq;
  axi_cfg_reg_sequence a_cfg_reg_seq;

  function new (string name=” axi_cfg_usb_bulk_virtual_sequence”,
                uvm_component parent=null);
    …
  endfunction: new

  task body();
    …
    //executingnon-virtual sequence on the corresponding
    //non-virtual sequencer using `uvm_do_on
    `uvm_do_on(a_cfg_reg_seq, p_sequencer.axi_seqr)
    a_cfg_req_seq.get_response();
    `uvm_do_on(u_bulk_seq, p_sequencer.usb_seqr)
    u_bulk_seq.get_response();
  endtask: body

endclass: axi_cfg_usb_bulk_virtual_sequence

In the above virtual sequence, we are executing axi_cfg_reg_sequence and then usb_complex_sequence. Now having virtual sequence and virtual sequencer ready, let’s see how we can execute this virtual sequence from the top-level test.

//Top-level test where virtual sequence is set to virtual sequencer
class axi_cfg_usb_bulk_test extends uvm_test;
  …
  virtual function void build_phase(uvm_phase phase );
    …

    //Configuring variables in underlying sequences
    uvm_config_db#(int unsigned)::set(this,
      ”env.sys_vir_seqr.axi_cfg_usb_bulk_virtual_sequence.u_bulk_sequence”,
      ”sequence_length”,10);

    //Executing the virtual sequences in virtual sequencer’s 
    //appropriate phase.
    //Executing reset virtual sequence in reset_phase
    uvm_config_db#(uvm_object_wrapper)::set(this,
             "env.sys_vir_seqr.reset_phase", "default_sequence",
             axi_usb_reset_virtual_sequence::type_id::get());

    //Executing the main virtual sequence in main_phase
    uvm_config_db#(uvm_object_wrapper)::set(this,
                     "env.sys_vir_seqr.main_phase", "default_sequence",
                     axi_cfg_usb_bulk_virtual_sequence::type_id::get());
    …
  endfunction : build_phase
endclass

Until now we understood why and how we can use virtual sequences. We should also keep few things in mind while using virtual sequence and virtual sequencer to save a lot of debugging time.

1. While configuring the variables in the sequences (which are executed using virtual sequences) we have to use path thru virtual sequence. In above example, using the non-virtual sequencer path for setting the variables in the lower level sequence, will not work.

uvm_config_db#(int unsigned)::set(this,”env.usb_host_agent_obj.sequencer.u_bulk_sequence”,”sequence_length”,10);

Even though u_bulk_sequence is running on the usb_host_agent_obj.sequencer, this will not work because this sequence is created by the virtual sequence and hence hierarchal path should be from virtual sequence but not using non-virtual sequencer. So the right way of setting variables is using the virtual sequence path.

uvm_config_db#(int unsigned)::set(this,”env.sys_vir_seqr.axi_cfg_usb_bulk_virtual_sequence.u_bulk_sequence”,”sequence_length”,10);

This is also true for factory overrides. For example below factory override will not work for the same above reason.

set_inst_override_by_type(”env.usb_host_agent_obj.*”,usb_transfer_item::get_type(), cust_usb_transfer_item::get_type());

In the above example we are trying to change the underlying sequence item with a new derived type from top-level test. For doing this we need to use the virtual sequencer path.

set_inst_override_by_type(”env.sys_vir_seqr.*”,usb_transfer_item::get_type(), cust_usb_transfer_item::get_type());

Rules of Thumb are:
• If the sequence is created by a virtual sequence directly or indirectly, then any hierarchical path in factory overrides or in configurations should use virtual sequencer’s hierarchical path.
• If the sequence is created by a non-virtual sequence, then any hierarchical path in factory overrides or configurations should use non-virtual sequencer’s hierarchical path.

2. Even though we have virtual sequencer to control multiple sequencers, in some tests, we may just need a single sequencer (for example USB sequencer alone). In such cases, we have to use the non-virtual sequencer’s hierarchical path directly (not the virtual sequencer’s reference path) for configuring the variables or factory overrides. Using the virtual sequencer’s reference path will not work as the hierarchy of non-virtual sequencer is incorrect.

uvm_config_db#(uvm_object_wrapper)::set(this, “env.sys_vir_seqr.usb_seqr.main_phase”, “default_sequence”, usb_complex_sequence::type_id::get());

Above configuration will not work, as non-virtual sequencer (usb_seqr/usb_host_agent_obj.sequencer) is actually created in the agent, so the parent for this sequencer is agent but not the virtual sequencer, though the reference is in virtual sequencer. Hence we should not use virtual sequencer path when trying to set variables in the actual sequencer, instead we have to use the hierarchical path through the agent (actual parent to the sequencer).

uvm_config_db#(uvm_object_wrapper)::set(this, “env.usb_host_agent_obj.sequencer.main_phase”, “default_sequence”, usb_complex_sequence::type_id::get());

3. Whenever we are using virtual sequencer and want to control non-virtual sequencers from virtual sequencer, make sure to set the default_sequence in all the actual sequencers to null.

uvm_config_db#(uvm_object_wrapper)::set(this, “env.usb_host_agent_obj.sequencer.main_phase”, “default_sequence”, null);
uvm_config_db#(uvm_object_wrapper)::set(this, “env.axi_master_agent_obj.sequencer.main_phase”, “default_sequence”, null);

This is important because if there is any default_sequence set, then our non-virtual sequencer will be running both the default_sequence and the sequence from the virtual sequence. To control non-virtual sequencers solely from virtual sequencer, we need to set the default_sequence of the non-virtual sequencers as null.

I hope you find this post useful for understanding virtual sequences and save debugging time with the guidelines outlined. I am sure there will be other guidelines while using virtual sequences, which we learn the harder way debugging complex environments; please share any such guidelines with me.

Authored by Hari Balisetty, Broadcom

Here’s where you can find more information on our Verification IP.

Posted in AMBA, Debug, Methodology, MIPI, SystemVerilog, USB, UVM | No Comments »

Reusable Sequences in UVM

Posted by VIP Experts on March 26th, 2015

In this blog, I describe the necessary steps one has to take while writing a sequence to make sure it can be reusable. Personally, I feel writing sequences is the most challenging part in verifying any IP. Careful planning is required to write sequences without which we end up writing one sequence for every scenario from scratch. This makes sequences hard to maintain and debug.

Here’s where you can find more information on our Verification IP.

As we know, sequences are made up of several data items, which together form an interesting scenario. Sequences can be hierarchical thereby creating more complex scenarios. In its simplest form, a sequence should be a derivative of the uvm_sequence base class by specifying request and response item type parameter and implement body task with the specific scenario you want to execute.

class usb_simple_sequence extends uvm_sequence #(usb_transfer);

    rand int unsigned sequence_length;
    constraint reasonable_seq_len { sequence_length < 10 };

    //Constructor
    function new(string name=”usb_simple_bulk_sequence”);
        super.new(name);
    endfunction

   //Register with factory
   `uvm_object_utils(usb_simple_bulk_sequence)

   //the body() task is the actual logic of the sequence
   virtual task body();
      repeat(sequence_length)
      `uvm_do_with(req,  {
      //Setting the device_id to 2
          req.device_id == 8’d2;
          //Setting transfer type to BULK
          req.type == usb_transfer::BULK_TRANSFER;
       })
   endtask : body
endclass

In the above sequence we are trying to send usb bulk transfer to a device whose id is 2. Test writers can invoke this by just assigning this sequence to the default sequence of the sequencer in the top-level test.

class usb_simple_bulk_test extends uvm_test;

…
    virtual function void build_phase(uvm_phase phase );
        …
        uvm_config_db#(uvm_object_wrapper)::set(this, "sequencer_obj.
        main_phase","default_sequence", usb_simple_sequence::type_id::get());
        …
    endfunction : build_phase
endclass

 

So far, things look simple and straight forward. To make sure the sequence is reusable for more complex scenarios, we have to follow a few more guidelines.

  • First off, it is important to manage the end of test by raising and dropping objections in the pre_start and post_start tasks in the sequence class. This way we raise and drop objection only in the top most sequence instead of doing it for all the sub sequences.
task pre_start()

    if(starting_phase != null)
    starting_phase.raise_objection(this);
endtask : pre_start

task post_start()

    if(starting_phase != null)
    starting_phase.drop_objection(this);
endtask : post_start

Note that starting_phase is defined only for the sequence which is started as the default sequence for a particular phase. If you have started it explicitly by calling the sequence’s start method then it is the user’s responsibility to set the starting_phase.

class usb_simple_bulk_test extends uvm_test;

    usb_simple_sequence seq;
    …
    virtual function void main_phase(uvm_phase phase );
        …
        //User need to set the starting_phase as sequence start method
        is explicitly called to invoke the sequence
        seq.starting_phase = phase;
        seq.start();
        …
    endfunction : main_phase

endclass

  • Use UVM configurations to get the values from top level test. In the above example there is no controllability given to test writers as the sequence is not using configurations to take values from the top level test or sequence (which will be using this sequence to build a complex scenario). Modifying the sequence to give more control to the top level test or sequence which is using this simple sequence.
class usb_simple_sequence extends uvm_sequence #(usb_transfer);

    rand int unsigned sequence_length;
    constraint reasonable_seq_len { sequence_length < 10 };
    …
    virtual task body();
        usb_transfer::type_enum local_type;
        bit[7:0] local_device_id;
        //Get the values for the variables in case toplevel
         //test/sequence sets it.
        uvm_config_db#(int unsigned)::get(null, get_full_name(),
            “sequence_length”, sequence_length);
        uvm_config_db#(usb_transfer::type_enum)::get(null,
            get_full_name(), “local_type”, local_type);
        uvm_config_db#(bit[7:0])::get(null, get_full_name(),?
            “local_device_id”, local_device_id);
        repeat(sequence_length)
        `uvm_do_with(req, {
            req.device_id == local_device_id;
            req.type == local_type;
        })
    endtask : body

endclass

With the above modifications we have given control to the top-level test or sequence to modify the device_id, sequence_length and type. A few things to note here: the parameter type and string (third argument) used in uvm_config_db#()::set should be matching the type being used in uvm_config_db#()::get. Make sure to ‘set’ and ‘get’ with exact datatype. Otherwise value will not get set properly, and debugging will become a nightmare.

One problem with the above sequence is: if there are any constraints in the usb_transfer class on device_id or type, then this will restrict the top-level test or sequence to make sure it is within the constraint.

For example if there is a constraint on the device_id in the usb_transfer class, constraining it to be below 10 then top-level test or sequence should constraint it, within this range. If the top-level test or sequence sets it to a value like 15 (which is over 10) then you will see a constraint failure during runtime.

Sometimes the top-level test or sequence may need to take full control, and may not want to enable the constraints which are defined inside the lower level sequences or data items. One example where this is required is negative testing:- the host wants to make sure devices are not responding to the transfer with a device_id greater than 10 and so wants to send a transfer with device_id 15. So to give full control to the top-level test or sequence, we can modify the body task as shown below:

virtual task body();

    usb_transfer::type_enum local_type;
    bit[7:0] local_device_id;
    int status_seq_len = 0;
    int status_type = 0;
    int status_device_id = 0;
    status_seq_len = uvm_config_db#(int unsigned)::get(null,
        get_full_name(), “sequence_length”, sequence_length);
    status_type = uvm_config_db#(usb_transfer::type_enum)::get(null,
        get_full_name(),“local_type”,local_type);
    status_device_id = uvm_config_db#(bit[7:0])::get(null,
        get_full_name(), “local_device_id”,local_device_id);
    //If status of uvm_config_db::get is true then try to use the values
        // set by toplevel test or sequence instead of the random value.
    if(status_device_id || status_type)
    begin
        `uvm_create(req)
        req.randomize();
        if(status_type)
        begin
        //Using the value set by top level test or sequence
        //instead of the random value.
            req.type = local_type;
        end
        if(status_device_id)
        begin
            //Using the value set by top level test or sequence
        //instead of the random value.
            req.device_id = local_device_id;
        end
    end
    repeat(sequence_length)
        `uvm_send(req)

endtask : body

It is always good to be cautious while using `uvm_do_with as it will add the constraints on top of any existing constraints in a lower level sequence or sequence item.

Also note that if you have more variables to ‘set’ and ‘get’ then I recommend you create the object and set the values in the created object, and then set this object using uvm_config_db from the top-level test/sequence (instead of setting each and every variable inside this object explicitly). This way we can improve runtime performance by not searching each and every variable (when we execute uvm_config_db::get) , and instead get all variables in one shot using the object.

virtual task body();

    usb_simple_sequence local_obj;
    int status = 0;
    status = uvm_config_db#usb_simple_sequence)::get(null,
        get_full_name(),“local_obj”,local_obj);
    //If status of uvm_config_db::get is true then try to use
    //the values set in the object we received.
    if(status)
    begin
        `uvm_create(req)
        this.sequence_length = local_obj.sequence_length;
        //Copy the entire req object inside the object which we
        //received from uvm_config_db to the local req.
        req.copy (local_obj.req);
    end
    else
    begin
        //If we did not get the object from top level sequence/test
        //then create one and randomize it.
        `uvm_create(req)
        req.randomize();
    end
    repeat(sequence_length)
        `uvm_send(req)

endtask : body

  • Always try to reuse the simple sequences by creating a top level sequence for complex scenarios. For example, in below sequence am trying to send bulk transfer followed by an interrupt transfer to 2 different devices. For this scenario I will be using our usb_simple_sequence as shown below:
class usb_complex_sequence extends uvm_sequence #(usb_transfer);

    //Object of simple sequence used for sending bulk transfer
    usb_simple_sequence simp_seq_bulk;
    //Object of simple sequence used for sending interrupt transfer
    usb_simple_sequence simp_seq_int;
    …
    virtual task body();
        //Variable for getting device_id for bulk transfer
        bit[7:0] local_device_id_bulk;
        //Variable for getting device_id for interrupt transfer
        bit[7:0] local_device_id_int;
        //Variable for getting sequence length for bulk
        int unsigned local_seq_len_bulk;
        //Variable for getting sequence length for interrupt
        int unsigned local_seq_len_int;
        //Get the values for the variables in case top level
        //test/sequence sets it.
        uvm_config_db#(int unsigned)::get(null, get_full_name(),
        “local_seq_len_bulk”,local_seq_len_bulk);
        uvm_config_db#(int unsigned)::get(null, get_full_name(),
        “local_seq_len_int”,local_seq_len_int);
        uvm_config_db#(bit[7:0])::get(null, get_full_name(),
        “local_device_id_bulk”,local_device_id_bulk);
        uvm_config_db#(bit[7:0])::get(null, get_full_name(),
        “local_device_id_int”,local_device_id_int);
        //Set the values for the variables to the lowerlevel
        //sequence/sequence item, which we got from
        //above uvm_config_db::get.
        //Setting the values for bulk sequence
        uvm_config_db#(int unsigned)::set(null, {get_full_name(),”.”,
        ”simp_seq_bulk”}, “sequence_length”,local_seq_len_bulk);
        uvm_config_db#(usb_transfer::type_enum)::set(null, {get_full_name(),
        “.”,“simp_seq_bulk”} , “local_type”,usb_transfer::BULK_TRANSFER);
        uvm_config_db#(bit[7:0])::set(null, {get_full_name(), “.”,
        ”simp_seq_bulk”}, “local_device_id”,local_device_id_bulk);
        //Setting the values for interrupt sequence
        uvm_config_db#(int unsigned)::set(null, {get_full_name(),”.”,
        ”simp_seq_int”}, “sequence_length”,local_ seq_len_int);
        uvm_config_db#(usb_transfer::type_enum)::set(null, {get_full_name(),
        “.”,“simp_seq_int”} , “local_type”,usb_transfer::INT_TRANSFER);
        uvm_config_db#(bit[7:0])::set(null,{get_full_name(),“.”,
        ”simp_seq_bulk”},“local_device_id”,local_device_id_int);
        `uvm_do(simp_seq_bulk)
        simp_seq_bulk.get_response();
        `uvm_send(simp_seq_int)
        simp_seq_int.get_response();
    endtask : body

endclass

Note that in the above sequence, we get the values using uvm_config_db::get from the top level test or sequence, and then we set it to a lower level sequence again using uvm_config_db::set. This is important without this if we try to use `uvm_do_with and pass the values inside the constraint block then this will be applied as an additional constraint instead of setting these values.

I came across these guidelines and learned them, at times the hard way. I sure hope these will come in handy when you use sequences that come pre-packed with VIPs to build more complex scenarios, and also when you wish to write your own sequences from scratch. If you come across more such guidelines or rules of thumb for writing re-usable, maintainable and debuggable sequences, please share them with me.

Authored by Hari Balisetty, Broadcom

Here’s where you can find more information on our Verification IP

Posted in Debug, Methodology, SystemVerilog, USB, UVM | No Comments »

Ins and outs of SS Link Training in USB3.0

Posted by VIP Experts on March 24th, 2015

As you may know, USB3.0 has a state machine called LTSSM (Link training and status state machine) which is responsible for

  1. Initialization and link training
  2. Power management transitions
  3. Link error recovery and other connectivity issues.

Here’s where you can find more information on our Verification IP.

LTSSM has 12 high level states as shown below. In this blog, we will examine the states that are involved in link training, and see how link partners moves to state U0 where actual transfers begin.

Link training is the sequence of events which takes place during the initialization of link after power on reset or when warm reset is directed. This is basically to detect the link partner and train the link before starting to do any kind of transfers on the link. As shown in above diagram, the link training sequence starts at Rx.Detect  (the power ON state for  both an upstream port and a downstream port), and ends with exit to U0 which is the normal operation state where packets are transmitted and received. Before link training, both upstream and downstream ports will be in SS.Disabled state (the state where a port’s SuperSpeed connectivity is removed). In the Polling state, link training is enabled through the LFPS (Low Frequency Periodic Signal) handshake used to communicate information without SS signaling

The following figure shows the link training states along with their sub-states.

How do you configure your Verification IP for completing the SuperSpeed link training sequence in lock step with the DUT?  Synopsys’ USB 3.0 and 3.1 Verification IPs define several timers and parameters with the appropriate default values which makes it a simple task to achieve this. Some of these parameters map to the USB specification and a few are added to aid the verification of the operation of the DUT in both normal or error conditions. The default values ensure that you can enable the Link Training sequence without having to override any of the parameter values.

In some cases you may need to tweak the parameters to try out different corner cases or to further slow down the time taken for link training. Here, we will specifically look at the link training sequence (due to warm reset or power on reset) and will correlate the parameters in the VIP which affect this sequence.

All the names mentioned in italics are variables in svt_usb_configuration class in USB VIP, names/values in square brackets [] are USB specification names/values.  If the direction of port is not mentioned it is taken to be for both upstream (host) and downstream (device) port.

Rx.Detect.Reset

Entry to this state can happen because of a warm reset or a power on reset. Watch out for the parameters below as physical power goes to P2 state. Depending on the previous physical power state, the VIP uses one (or more) of the below timer value.

  • p0_to_p2_transition_time
  • p3_to_p2_transition_time
  • p3_to_p0_transition_time
  • allow_p2_p3_direct_transition

If the entry is not due to warm reset then it moves directly to Rx.Detect.Active. If the entry is due to Warm Reset then the transition depends upon the type of the port VIP is configured as.

  • If the VIP is configured as a downstream port (host) then it transmits LFPS for t_reset_timeout [tReset] time. This is called as warm reset sequence. As soon as timer expires, the VIP stops sending LFPS and moves to Rx.Detect.Active.
  • If the VIP is configured as an upstream port (device) then transition to Rx.Detect.Active happens after host (DUT connected to VIP) completes sending LFPS warm reset signaling.

Rx.Detect.Active

This state is used for detecting the link partner at the other end. In this state, the VIP performs ‘receiver termination’ detection (receiver_detect_time) and moves to Polling.LFPS, if ‘receiver termination’ is detected. If the receiver termination is not detected then it does the following.

  • If VIP is a downstream port (host) then it moves to Rx.Detect.Quiet.
  • If VIP is an upstream port (device) then it moves to Rx.Detect.Quiet for rx_detect_termination_detect_count [8] times. If low impedance termination is not detected even after this then moves to SS.Disabled.

NOTE: ‘Receiver termination’ is detected differently in serial vs PIPE3 interface.

Rx.Detect.Quiet

Wait here until rx_detect_quiet_timeout [12ms timer] expires and move back to Rx.Detect.Active.

Figure 1: LFPS signalling in Polling.LFPS

Polling.LFPS

Once the link partner is detected in Rx.Detect state, both (upstream and downstream) ports go into Polling for training the link. In this state, the VIP transmits LFPS until burst timer polling_lfps_burst_time) expires. It also counts the number of bursts received and checks if the exit criteria (check below for exit criteria) are met. If the exit criteria are not met, then the VIP would wait for the ‘repeat timer’ (polling_lfps_repeat_time) to expire and then start the above process (transmitting LFPS) again.

Exit Criteria for exiting to Polling.RxEq.

  • polling_lfps_sent_count (no. of LFPS bursts sent) [16]
  • polling_lfps_received_count (no. of LFPS received) [2]
  • polling_lfps_sent_after_received_count (no. of LFPS bursts sent after receiving first LFPS from the link partner) [4]

It is important to meet the exit criteria before polling_lfps_timeout [360ms timer] expires. If timeout expires then VIP does one of the following depending on the direction of the port

  • If downstream port (Host) then it moves to Rx.Detect
  • If upstream port (Device) then it moves to SS.Disabled

Figure 2: TSEQ getting exchanged during Polling.RxEq

Polling.RxEq

This state is used to train equalization logic by exchanging TSEQ (Equalization Training Sequence) ordered sets. One can skip this state by enabling ltssm_skip_polling_rxeq. After transmitting polling_rxeq_tseq_count [65,536] number of TSEQ ordered sets VIP will move to Polling.Active.

Polling.Active

In this state, the VIP will keep on sending TS1’s until it receives polling_active_received_ts_count number of TS1/TS2 continuously. Every time a different sequence is received, the VIP will reset the counter. Thus, it makes sure either TS1 or TS2’s are received continuously for polling_active_received_ts_count [8] number of times.

It is important to meet the exit criteria before polling_active_timeout [12ms timer] expires. If this timeout expires, then the VIP does one of the following:

  • If it’s a downstream port (Host),  it would  move to Rx.Detect
  • If it’s an upstream port (Device), then it would move to SS.Disabled.

Figure 3: TS1 and TS2 getting exchanged in Polling.Active and Polling.Configuration

Polling.Configuration

In this state, the VIP will start sending TS2’s but will only start counting them after receiving the first TS2 from the link partner.

Exit Criteria: This state is exited once the following counts are met.

  • polling_configuration_received_ts2_count [8] //No. of TS2 received
  • polling_configuration_sent_ts2_count [16] //No. of TS2’s sent after receiving the first TS2 from the link partner

It is important to meet the exit criteria before polling_configuration_timeout [12ms timer] expires. If timeout expires then the VIP does one of the following

  • If it is a downstream port (Host), it moves to Rx.Detect
  • If it is a upstream port (Device, it moves to SS.Disabled.

Polling.Idle

First thing that the VIP does in this state is to check if the reset bit is set in the TS2’s received in Polling.Configuration and if the port direction is upstream (device). If it detects these two conditions, the VIP moves directly to Hot.Reset state of LTSSM.

If above condition is false then exit to U0 when below ‘counts’ are reached.

  • polling_idle_received_idle_count [8] // No. of idle’s received
  • polling_idle_sent_idle_count [16]      // No.  of idle’s sent after receiving the first idle from the link partner.

The important point here is to meet the exit criteria before polling_idle_timeout [2ms timer] expires. If timeout expires then the VIP does one of the following

  • If downstream port (Host) then move to Rx.Detect
  • If upstream port (Device) then move to SS.Disabled.

Figure 4: U0 state at the end of link training

Once Polling.Idle is done, link moves to U0 state where physical power changes to P0 and the actual transfers starts. Thru out this sequence at any given point of time, upstream port (device) moves to Rx.Detect on warm reset. Most VIP’s has an option to start in U0 state (usb_ss_initial_ltssm_state) so that users can skip entire initial link training and can start doing the transfers right from the start of simulation. Sometimes the DUT which is connected to VIP may not have such option to skip link training, in those cases we recommend to play with the configuration parameters mentioned in this blog to minimize the simulation time in link training.

We hope this blog post helps you to plan out your different link training sequences as per your needs.

Authored by Hari Balisetty, Broadcom

Here’s where you can find more information on our Verification IP

Posted in Methodology, SystemVerilog, USB | No Comments »

How do you Verify the AMBA System Level Environment?

Posted by VIP Experts on March 19th, 2015

In my previous blog, AMBA based Subsystems: What does it take to verify them?, I had discussed some of the key verification challenges when it comes to verifying complex SOCs based on AMBA based subsystems. It was observed that it would indeed be useful to have an extensible AMBA based verification environment which can be tweaked minimally so that it can be reused for new systems or derivatives.

To enable SOC verification engineers to create highly configurable AMBA fabric, the system environment should provide place-holders for hooking the DUT with any of the quintessential AMBA VIP components such as AXI3/4/ACE, AHB or APB. With the use of AMBA System environment we can configure it to instantiate as many number of AXI/AHB/APB VIP with minimal additional code. Thus, such an environment would need to encapsulate the following among others:

  • CHI system environment
  • AXI (3/4/ACE) system environment
  • AHB system environment
  • APB system environment
  • A virtual sequencer
  • An array of AMBA System Monitors
  • Configuration descriptor of the AMBA system environment which can be used to configure the underlying CHI/AXI/AHB/APB System environment

The figure below shows a representation of such a verification environment:

AMBA-System-Env

Let’s see what features in UVM can come in handy for creating a robust environment for some of the important system level capabilities:

  • Layered virtual sequencers to achieve synchronization between various components: A system sequencer which manages synchronization across the bus fabric can be modeled as a virtual sequencer with references to the virtual sequencers within CHI System Env, AXI System Env, AHB System Env and APB System Env.
  • Leveraging Analysis ports for system level checks, score boarding and response handling: Each of the Port Monitors in the CHI, AXI, AHB & APB Master and Slave Agent would ideally have an analysis port. At the end of the transaction, the Master and Slave Agents respectively write the completed transaction object to the analysis port. Such upstream ports and downstream ports can be specified to be used by the system monitor to track transformations and responses across the fabric as well as to perform routing checks.
  •  Using callbacks to enable user extensions and to extract coverage and throughput measurement: Callbacks are an access mechanism that enable the insertion of user-defined code and allow access to objects for performance analysis and throughput measurements in the case of the AMBA system environment.
  • A comprehensive sequence library to be run on the virtual sequencer in the System environment: UVM allows for a logical collection of sequences to be registered to a sequence library and this collection can execute on an associated sequencer. A system level sequencer then coordinates the execution of these collection of sequences across different sequencers to create an interesting mix of scenarios while targeting the maximum coverage for a system level stimulus perspective

From a verification perspective, system level checks are key. As mentioned earlier, they can include:

  •  Data Integrity checks across CHI, AXI, AHB and APB ports
  •  Transaction routing checks across CHI, AXI, AHB and APB ports

In my next blog, I will talk about this aspect in more detail. I would walk you through the capabilities that you would need in your System monitor to easily perform the checks mentioned above.

Authored by Satyapriya Acharya 

Here’s where you can find more information on Verification IP for AMBA 4 AXI.

Posted in AMBA, Methodology, SystemVerilog, UVM | No Comments »

Programming AXI-ACE VIP to Generate Error Scenarios

Posted by VIP Experts on March 17th, 2015

VIP manager Tushar Mattu of Synopsys describes how to program  AXI-ACE VIP to generate error scenarios

For more information, please check out Verification IP for AMBA 4 AXI.

Posted in AMBA, Debug, SystemVerilog, UVM | No Comments »

How to Integrate uvm_reg with AXI VIP

Posted by VIP Experts on March 12th, 2015

VIP manager Tushar Mattu of Synopsys gives insights on how to effectively integrate uvm_reg with AXI VIP http://bit.ly/1xboMLS

For more information, please check out Verification IP for AMBA 4 AXI.

Posted in AMBA, Methodology, SystemVerilog, UVM | No Comments »

Start using AXI VIP with some basic understanding of UVM

Posted by VIP Experts on March 10th, 2015

Recently I worked with a user who was responsible for verifying an AXI interface. This user did not have a UVM background, but was conversant with SystemVerilog. The user was faced with the challenge of learning UVM as well as coming up to speed with an understanding of the VIP: both at the same time, under tight verification timelines. Figuring out how much UVM knowledge would suffice to integrate the VIP, then coding the testbench around the VIP to run and debug the verification environment, appeared to be the first few challenges. I proposed a simple approach: let us begin with a simple directed testbench, get some AXI tests going using the VIP, gain some confidence in terms of understanding the core functionality of the DUT and VIP, and then, in parallel, learn some UVM basics as well. Later, I suggested, he can move on to advanced testing using constrained-random verification where he will need more advanced UVM knowledge, for instance, the application of virtual sequences.

Here’s where you can find more information on Synopsys’ Verification IP for AMBA 4 AXI.

Here are the steps used to integrate AXI VIP to start verification of an AXI interface in a simple directed environment. This approach for directed testing achieves good performance as well.

The testbench example below shows one AXI master VIP connected to a DUT slave. The actual example also uses a VIP in lieu of a slave DUT.

1) Import and include required VIP packages/files

Synopsys’ VIPs are delivered as SystemVerilog packages. These packages define a unique namespace for the VIP, but to make the VIP easier to use, the VIP namespace can be imported into the global namespace. In addition to SystemVerilog packages, some aspects of SVT VIPs such as SystemVerilog interfaces are delivered as global files that must be included because they must exist in both the design and testbench domain.

`include "uvm_pkg.sv"
`include "svt_axi_if.svi"

/** Include the AXI SVT UVM package */
`include "svt_axi.uvm.pkg"

module test_top;
/** Import UVM Package */
import uvm_pkg::*;
/** Import the SVT UVM Package */
import svt_uvm_pkg::*;
/** Import the AXI VIP */
import svt_axi_uvm_pkg::*;
…
…
endmodule


2) Connect the VIP Interface to the DUT signals

VIPs are delivered with SystemVerilog interfaces which provide the signal connectivity required. An instance of these interfaces must be declared and the signals from these interfaces must be connected to the DUT. Here in this example both the master(vip) and the slave(vip) are connected back to back. One can easily replace the required VIP model with corresponding DUT model.

  /** VIP Interface instance representing the AXI bus */
  svt_axi_if axi_if();
  assign axi_if.common_aclk = SystemClock;

  /** Testbench reset */
  logic tb_reset;

  /**
   * Assign the testbench reset to the reset pins of the VIP
   * interface.
   */
  assign axi_if.master_if[0].aresetn = tb_reset;

  /* connection from master[0] to slave[0], connected back to back */
  assign axi_if.slave_if[0].awvalid = axi_if.master_if[0].awvalid;
  assign axi_if.slave_if[0].awaddr = axi_if.master_if[0].awaddr;
  …
  assign axi_if.master_if[0].arready = axi_if.slave_if[0].arready;
  assign axi_if.master_if[0].rvalid = axi_if.slave_if[0].rvalid;
  assign axi_if.master_if[0].rlast = axi_if.slave_if[0].rlast;
  …
  …
/** make rest of assignments (you can alternately choose the SystemVerilog bind approach
/** for that you can refer to “amba_svt/tb_axi_svt_uvm_intermediate_sys”
/** example from VIP installation

3) Create dummy UVM test for objection management and UVM low execution

Directed_test is a dummy test, which extends uvm_test. This allows the UVM phasing mechanism to execute, and manages the objection from the run phase for a directed test written in a procedural block using an event (end_test) synchronization.

class Directed_test extends uvm_test;

   /** UVM Component Utility macro */
  `uvm_component_utils(Directed_test)

   /** Class Constructor */
  function new(string name = "Directed_test", uvm_component parent=null);
    super.new(name,parent);
  endfunction: new

  //Objection management co-ordinated by uvm_test
  virtual task run_phase(uvm_phase phase);
      super.run_phase(phase);
      phase.raise_objection(this);
      @end_test;  //this event will be triggered by directed test from initial-begin-end block
      phase.drop_objection(this);
  endtask

endclass

4) Instantiate the VIP components

The master and slave VIP agent classes must be constructed and configured. After initializing these configuration objects, they are sent to respective agent instances in the UVM hierarchy using the UVM resource database.

initial begin
   `uvm_info("Directed_test", "Entered...", UVM_MEDIUM)

    master_0 = svt_axi_master_agent::type_id::create("master_0",null);

    master_cfg0 = svt_axi_port_configuration::type_id::create("master_cfg0",null);

   /** set required  interface for agent instances */
    master_cfg0.set_master_if(axi_if.master_if[0]);

  /** Program  agent configuration parameters  */
    master_cfg0.data_width = 256;

   /**Pass master and slave configuration using resource database */
    uvm_config_db#(svt_axi_port_configuration)::set(null, "*master_0", "cfg", master_cfg0);

5) Start UVM execution

The UVM run_test() method starts the UVM execution and the argument to it is used as default test to execute.

    /** Start the UVM execution */
    fork
       run_test("Directed_test");
    join_none

6) Reset the DUT
DUT reset code must be called/executed before executing any transaction.

     /* Reset logic */
    `uvm_info("reset_logic", "Entered...", UVM_LOW)
    tb_reset = 1'b1;
    repeat(10) @(posedge SystemClock);
    tb_reset = 1'b0;
    repeat(10) @(posedge SystemClock);
    tb_reset = 1'b1;
    `uvm_info("reset_logic", "Exiting...", UVM_LOW)

7) Initiate the traffic from Master

Now we’re ready to start creating transactions from the master. The example below creates a WRITE transaction, sets all required fields and sends it to VIP master driver using the execute_item() method.

/* Create and Send atomic transaction */
    `uvm_info("atomic_transation", "Entered...", UVM_MEDIUM)
    begin
      svt_axi_master_transaction axi_trans;

          axi_trans = new();
          axi_trans.port_cfg          = cfg.master_cfg[0];
          axi_trans.xact_type       = svt_axi_transaction::WRITE;
          axi_trans.addr                = 32'h0000_0000;
          axi_trans.burst_type     = svt_axi_transaction::INCR;
          axi_trans.burst_size      = svt_axi_transaction::BURST_SIZE_32BIT;
          axi_trans.atomic_type  = svt_axi_transaction::NORMAL;
          axi_trans.burst_length = 16;
          axi_trans.data                = new[axi_trans.burst_length];
          axi_trans.wstrb              = new[axi_trans.burst_length];

          /** Send the atomic write transaction */
         master_0.sequencer.execute_item(axi_trans);     //send axi transaction to driver

      `uvm_info("atomic_transation", "Ended...", UVM_MEDIUM)
    end

8 ) Trigger End of Test

The end_test event is used to enable the objection that was raised for the run_phase() to drop. This signals the end of the run phase, and the rest of the UVM phases will execute once the run phase is done. This signals the end of the test.

    //Trigger uvm end of test
    end_test;
   `uvm_info("Directed_test", "Exited...", UVM_MEDIUM)
end

Authored by Tushar Mattu

Here’s where you can find more information on Synopsys’ Verification IP for AMBA 4 AXI.

Posted in AMBA, Methodology, SystemVerilog, UVM | 1 Comment »

How to Use the AXI VIP Debug Port

Posted by VIP Experts on March 5th, 2015

VIP manager Tushar Mattu of Synopsys gives insights on how to effectively use the AXI VIP Debug Port  http://bit.ly/18QYPMs

For more info, please check out Verification IP for AMBA 4 AXI.

Posted in AMBA, Debug, Methodology, SystemVerilog, UVM | No Comments »

Power Management of PCIe PIPE Interface

Posted by VIP Experts on March 3rd, 2015

Lately we have seen a trend of serial data transfers in place of parallel data transfer for improved performance and data integrity. One example of this is the migration from PCI/PCI-X to PCI Express. A serial interface between two devices results in fewer number of pins per device package. This not only results in reduced chip and board design cost but also reduces board design complexity. As serial links can be clocked considerably faster than parallel links,  they would be  highly scalable in terms of performance.

However, to accelerate verification of PCI Express based sub-systems and to accelerate the PCI Express endpoint development time ,  PIPE (PHY Interface for the PCI Express Architecture) was defined by Intel and was published for industry review in 2002. PIPE is a standard interface defined between a PHY sub-layer which handles the lower levels of serial signaling and the Media Access Layer (MAC) which handles addressing/access control mechanisms. The following diagram illustrates the role PIPE plays in partitioning the PHY layer for PCI Express.

Partitioning Phy Layer

(Source:  PHY Interface for thePCI Express Architecture specification, Version 2.00)

With this interface, developers can validate their designs without having to worry about the analog circuitry associated with teh Phy interface.  For the MAC core verification, the PHY Bus Functional Model (BFM) would  be connected directly to it. Without PIPE, it would be required to have the PHY and Serdes (serializer/deserializer) combination along with the Root Complex BFM. Additionally, the user would have to ensure the correctness of the PHY and SerDes behavior as well with the serial interface.

Given the value of the PIPE interface, it is now being widely used. In our recent experiences, we have observed that the different power states in the PIPE interface can create some confusion with respect to their interpretation. This blog post and the next will throw some light on the different power states of this interface. Hopefully, this will lead to a better understanding of the same. The assumption here is that the reader has a high level understanding of PCIe LTSSM.

Power states of PIPE

The power management signals allow the PHY to minimize the power consumption.  Four power states, P0, P0s, P1, and P2 are defined for this interface. P0 state is the normal operational state for the PHY. One it transitions from P0 to a lower power state, the PHY can immediately take appropriate power saving measures.

All power states are represented by signals PowerDown [2:0](MAC output). The Bit representation is as follows:

2]   [1]   [0]                           Description

0       0      0                            P0, normal operation

0       0      1                            P0s, low recovery time latency, power saving state

0       1      0                            P1, longer recovery time latency, lower power state

0       1      1                            P2, lowest power state.

PIPE interface power state can be correlated with power state of LTSSM as mentioned in Base specification (Refer to PCI_Express_Base_r3.0_10Nov10).

  1. P0 is equivalent to LTSSM State where Data/Order Set can transfer
  2. P0s is equivalent to L0s of LTSSM
  3. P1 is equivalent to Disabled, all Detect , and L1.Idle  state of LTSSM
  4. P2 is equivalent to L2 of LTSSM

Power state transitions in PIPE

In states P0, P0s and P1, the PHY is required to keep PCLK operational. For all state transitions between these three states, the PHY indicates successful transition into the designated power state  by a single cycle assertion of PhyStatus.

There is a limited set of legal power state transitions that a MAC can cause the PHY to make. Referencing the main state diagram of the LTSSM in the base specification and the mapping of LTSSM states to PHY power states described in the preceding paragraphs, those legal transitions are:

  1. P0 to P0s
  2. P0 to P1
  3. P0 to P2
  4. P0s to P0
  5. P1 to P0
  6. P2 to P1

Given that we understand the valid power state transitions,  I would capture more details about the individual power states and all possible transitions in more detail in my subsequent blog.  Stay tuned.

You can get more information at Synopsys Verification IP and VC Verification IP Datasheet.

Authored by Saurabh Shrivastava

 

Posted in Methodology, PCIe | No Comments »

How to Integrate AXI VIP into a UVM Testbench

Posted by VIP Experts on February 26th, 2015

Here, Synopsys VIP manager Tushar Mattu describes how best we can integrate AXI VIP into a UVM Testbench:  http://bit.ly/1Ay3zfb 

For more info, please check out Verification IP for AMBA 4 AXI.

Posted in AMBA, SystemVerilog, UVM | No Comments »