Archive for the 'Shows and Events' Category

Earlier this week I had the pleasure attending the Freescale Technology Forum (FTF). I was there to present on the Synopsys AUTOSAR activities, but was able to get a front row seat during Rich Beyer’s key note. I must say, the first FTF key note back as a public company after their IPO in may, left me nothing less but impressed. It also made me think about who really owns the system-level knowledge these days.

Rich Beyer’s key note opened with a brief video history lesson of former Motorola and Freescale devices, to a heart-beat-like sound track, somewhat reminding of the drums in the Terminator soundtrack. Rich opened with a discussion of challenges presented by us – the end users. Specifically he talked about the internet of things, connected intelligence, devices which adapt to our needs, have all our data in a cloud and even predict what we may want to adapt to us users. In most segments Freescale’s customers were present as well – if not live on stage, then at least via videos.

The chips Freescale develops were always present somehow, but the main event was always their use in end applications. The five “Global Diamond Sponsors” were all embedded software companies: ENEA, Greenheils, Mentor Embedded, QNX and Wind River, testimony to the fact that hardware and software are getting closer.

Five key areas were presented on in more detail:

• Smart Mobile: Here it was all about tablets, cell phones and smart devices which are so easy to use “that my mom could use them”. The new quad-core Freescale i.MX6 series based on ARM Cortex A9 was demonstrated – about one week after silicon samples were back from the fab.
• Networking: This area was all about the infrastructure development. Which capital investment becoming almost unmanageable in this area, the new Alcatel Lucent lightRadio™ (one node in Rich;s hand above) was introduced, apparently distributing the towered basestations into  much smaller array of devices, reducing power and offering major savings for operators.
• Medical: Freescale presented a very cool combination of sensors – installed under the bed and measuring heart rate and turns – with apps on a tablet bringing all your medical data together and then communicating with the doctor via a robot user interface
• Smart Energy: Fujitsu announced a partnership with Freescale around the energy network in Japan, essentially monitoring the network to optimize energy consumption
• Automotive: A triple zero is a good thing in automotive! Freescale outlined a roadmap how to get to zero defects, zero emission and zero fatalities. Apps are involved as well – together with GM Freescale demonstrated apps for the Volt – switching it on and off, pre-conditioning the cockpit and sending information from Google Maps automatically to the guidance system in the car.

In all the areas it strongly looked to me that Freescale as semiconductor company has actually more system-level knowledge than I ever expected – hence the title of this post. It is very clear that the design chain from IP Providers, Semiconductors to Integrators and OEMs is undergoing fundamental changes. With IP Providers heading towards sub-systems and Semiconductor Providers taking on more system responsibility, it will be interesting to see how the design chain will look five years from now!

One thing is clear: Embedded software and system-level design together with tools and methodologies enabling them, will be a key enabler to facilitate whatever changes are ahead.

As a follow up to the DAC workshop called “Intra and Inter-Vehicle Networking in Automotive: Past, Present, and Future”, fellow Blogger Karen Bartelson and I had the pleasure of talking to Wilfired Steiner, Senior Research Engineer from TTTEch, about the challenges of the design of fault tolerant systems.

The discussion covers a variety of topics including the importance of standards, what can happen if real time systems like car’s are not fault tolerant, the design challenges, how the relationships between IP providers and semiconductor companies work, the role of software and we even touched on how much fun standardization can be. You can listen to the full discussion here at our archive of Conversation Central topics.

The technical item which fascinated me the most, is the way how TTTEch and the standardization teams have built on top of an existing standard – Ethernet – capabilities to make timing deterministic. Wilfired explains the details of how timing packets are used to synchronize all network participants in the video below. To reap the benefits, some of the infrastructure needs to be upgraded, but for example in a car the developer has the appropriate design control to account for this upgrade.

From a design tool’s perspective – the amount of software I those systems makes the use of early software development and techniques to enable it (like FPGA and Virtual Prototyping) basically mandatory. Wilfried commented on both simulation and formal techniques during the discussion we had.

It seems like BMW will start using Ethernet for rear view camera video transmission starting in some 2013 models … it will be interesting to see how the adoption of Ethernet and its extensions will evolve over the coming years.

The Mentor ESL panel took place in its 9th year on DAC Tuesday in front of a very big “free-lunch-audience”. Wally Rhines kicked off the event in his usual data-driven manner, identifying the three types of design disciplines encompassing the SoC Design process: First there are “Hardware Custom IP Designers” challenged to shorten IP development and verification lead times. Second there are “Software Developers” who need to reduce software development, optimization and verification lead times. The third group are “SoC Architects and Integrators” who are challenged to design the full SoC for performance, low power and scalability.

The next generation design challenges for ESL – the drivers – are multicore design requiring virtual prototyping, system power implications and constraints requiring more than just power optimization and verification re-use throughout the flow from TLM to RTL requiring more automation and efficiency.

Turning over a new leaf, Mentor did invite a more management oriented panel from semiconductor (3),  IP (1) and EDA (1) companies.

First on stage was Gadi Singer, Vice President at the Intel Architecture Group. He focused in his slides on HLS as a key step towards, but in his words called ESL three things – (1) necessary, (2) about time and (3) having not enough critical mass yet to become the next level of design entry. At Intel ESL is considered a long-term must have, it s being used for pre-silicon software development and post silicon readiness. There are several internal activities on HLS, but for broad deployment of HLS, several technical issues still need to be addressed. Among them are standards, improved ECO flows, better ESL model validation, formal equivalence capacity between TLM and RTL, SystemC linting and an effective integration between HLS written code and hand written RTL.

John Goodenough, Vice President of Design Technology and Automation at ARM  talked about a “software first, sorry,hardware second” approach to ESL, somewhat apologetic towards the mostly hardware oriented audience. He mentiones several use cases including apps development pre and post silicon, architecture exploration, SoC design and validation and of course pre-silicon software bring up. Interoperability is crucial for ARM, SystemC offers some good starting points, but John also pointed out the still existing dilemma of running fast enough while providing enough accuracy on bus transactions.

Next up was Ken Hansen, Sr. Fellow, Vice president end Chief Technology Officer at Freescale Semiconductor. He talked about Freescale’s efforts to improve product differentiation with architecture optimization, software bring-up on virtual prototypes and co-design of hardware and software. As challenges to broader adoption he identified model availability and modeling expense, together with tool cost both for software developers and traditional EDA hardware users. He also commented on technical issues required for further proliferation, including better power  modeling, automation of back annotation from implementation data and more seamless flows between virtual and hardware execution.

Jean-Marc Chateau, Director of System Platforms and Tools at STMicroelectronics, briefly reviewed the history of ESL adoption in ST since 2002 starting with C based hardware verification before IP RTL is frozen to pre-RTL software testing and debug for subsystems in 2008 to full pre-silicon software availability since 2011. As next frontier he sees specification level models, methodologies and standards.

Representing the EDA Industry, Simon Bloch, Vice President and General Manager, ESL/HDL Design and Synthesis Division at Mentor Graphics described TLM level flows from modeling of blocks to assembly, virtual prototyping, debug and optimization and then finally re-use of TLM models both for HLS implementation and hardware verification. Simon identified software validation as leading ESL driver from Mentor’s survey, followed by faster verification for fewer bugs and faster time to verified RTL (see graph on the left).

In the subsequent discussion moderated by Wally, all panelists seemed to be quite optimistic about actual ESL adoption. Especially virtual prototyping for software development got high marks from Intel, Freescale and ST. High-Level Synthesis also enjoys quite some attention. ARM identified model speed as basic issue for lack of deployment in software development, closely followed by cost. There was quite some discussion about the cost of the model development and who can actually do the modeling. Intel, Freescale and ST seem to employ specialists team to do the modeling for both internal and external use.

Overall, as concluded by Wally, management – at least on this panel – does not seem to be the problem for ESL adoption.

No, not social networking in cars. I’ll leave that for a different time … This is about data and control carrying networks in cars and where they are going. Yesterday I attended here at DAC the Sunday workshop on “Intra and Inter-Vehicle Networking in Automotive: Past, Present, and Future”. It seems like Ethernet has won the battle, albeit not for all areas in the car.

First of all, this workshop was well organized, very productive and interesting – a big thank you to Paolo, Arko and Haibo for putting it together, and of course Alberto Sangiovanni Vincentelli for his championship and guidance.

What networks in a car you may ask? Most of us have heard of CAN, but there is so much more as I learned in the run-up to this event. In this post here a picture from Renesas with some annotations from our team. There are really five busses to look at today:

• CAN – most spread network in the car, some limitations with 1 Mbps bandwidth and non-deterministic behavior under high load >60%.
• LIN – low cost bus for body applications with 19.2 Kbauds and a UART interface
• MOST – designed for multimedia using optical fiber with bandwidth up to 150 Mb/s
• FlexRay – high performance (10 Mbps), deterministic, and secure network, mainly used in X-by-wire, ADAS, and high performance applications
• Ethernet – mainly used for diagnostics today, high potential for more

The morning session of the workshop did the setup from the user side. Alberto Sangiovanni Vincentelli started the day off with an insightful key note on the mega trends. He also pre-counted Ethernet as “winning 5:1” when previewing the upcoming presentations of the day. One key take away of his key note was the trend to design which fully separates function and architecture, which enables OEMs to ‘sandwich” the Tier 1 suppliers more by overtaking a more significant portion of the functional design in software, which then can be mapped into existing ECUs if there is enough performance left. Alberto was adamant that safety critical areas should be separated fully from infotainment like video and audio, safety being the main driving issue.

Harman International continued with an insightful presentation on the AVB extensions for Ethernet – soon to be fully standardized, followed by Prof. Huss from the University of Darnstadt describing simTD, a field test in Germany for Car-to-X applications with very interesting trial results. Raj Rajkumar showed simulations from CMU’s trials on timing guarantees in Vehicle to Vehicle (V2V) networks. What I found most interesting was that CMUs simulation showed that to be effective, only 7% to 8% of the cars need to be equipped with V2V communication. Raj also showed an App, which self-parks Boss, the  autonomous driving car which won the Darpa challenge. This certainly will come in handy during Christmas shopping when it is available.

National Instruments complemented the presentation from Harman with more details on AVB for Ethernet, TTTech gave a great overview of the Ethernet extensions to make Ethernet ready for timing critical and fault tolerant use. Austriamicrosystems did present a future which will see a symbiosis for in-vehicle networks.

After the morning sessions had kicked off with the design issues around Ethernet and left me with the impression that Ethernet is winning for most areas, I kicked off the afternoon session with an overview of challenges and solutions spanning from AutoSAR based architecture analysis, through signal integrity issues when laying out the network, though Ethernet IP and software development for testing. Mentor followed with their AUTOSAR and harness related offerings, Cadence focused on Ethernet IP. Further design solutions for networking related architecture development were presented by aquintos/Vector and Mirabilis, Symtavision closed the day with an overview of migrating from CAN to FlexRay and Ethernet using their formal techniques for timing analysis.

Most valuable was the Q&A. I bluntly asked whether Ethernet is winning or not and the answer was “mostly”. Ethernet definitely has a bright future for video, audio and infotainment in general, but also for more timing critical applications. It’s only downside seem to be cost and EMC issues. FlexRay is definitely not dead it seems, as it used for some timing related applications still. I also asked what the next bus will be which we tool providers need to prepare for. One answer pointed to wireless protocols as next frontier, which makes sense, as weight of cables is a constant target for cost and fuel reduction. Finally I asked who will actually own the other side of the vehicle to infrastructure (V2I) networking as somebody needs to manage traffic and all the data collected. This seems to be an unclear issue and the parties involved in current field trials mentioned that the OEMs need to get together to stimulate that portion. Lots of government and regulatory issues are at play here. It might be easier to create this infrastructure in areas like China’s future megacities, which are just being  planned and built.

Overall a great workshop with interesting insights. Ethernet definitely seems to have a bright future in cars!

The embedded systems conference is a mystery to me. It always has been. And this year it has been the weirdest of all. A dinosaur? Really? Yes, really, I too the picture of “Samson” below …. Something is not right here. Aren’t they a sign of extinction? I must have missed something in my marketing class. Or the engineer in me is finally trying to break free again and does not get it. No wonder, according to the “Specimens of Tyrannosaurus” Wikpedia page, I also had missed the eBay auction in 2000 in which “Z-rex” was not sold for $8 million and then was subsequently renamed. Oh well.

While the technical conference program looked great – the tutorials have become the main attraction of ESC and are definitely worth their money – attendance on the show floor was light but steady, at least on Tuesday, when I attended for some analysts and partner meetings. Walking the show floor, the exhibitors varied from software programming, lifecycle tracking, compiler, OS, small and bigger board companies, chip and microcontroller vendors to the multi-core zone and the “close-to-embedded” EDA companies Mentor, Cadence and Synopsys.

We at Synopsys had a small booth, we focused on showing our FPGA prototyping, FPGA design tools as well as our embedded offerings around processor development and virtual prototypes. We did not make any announcements. Mentor was present with their “Mentor Embedded” division and announced their integrated development environment based on the GNU Toolchain based on the technology and tools previously acquired from CodeSourcery. In addition, Cadence announced what they call their System Development Suite.

At Synopsys we are serving the market needs of system designers and embedded software developers for a while now. We have made significant investments via several acquisitions. It is nice to see that another big EDA player now also follows and validates this market. The actual announcement was well executed and is naturally anchored on their strength of emulation and RTL simulation. Building on those incrementally the two elements of FPGA based and virtual prototyping, makes perfect sense from where they are at. We will see how a Linux-centric, “hardware-out” approach will work for users when the actual tools come out “later this year”. Undoubtedly the need for better system design tools and more productive software development is strong, as is the need for connections from the system-level to implementation and verification. Synopsys is just wrapping up a worldwide seminar series in which we demonstrated a complete systems to silicon verification solution.

At the end of ESC Mentor took home the VDC Embeddy Best Software Product award. And on Wednesday, just to close the loop back to dinosaurs and times long passed, something unexpected happened in San Jose. While I was happily (and slightly chilled) traveling in Ontario, temperatures in San Jose crept up enough to cause a rolling power black out. As I later heard via phone, my wife was in the midst of a press briefing when the conference center turned pitch black. The effects are nicely described by Bernhard Cole in his Editor’s Note at embedded.com. I guess the only one happy and comfortable in his natural, electricity-free habitat, was probably Samson …

The bottom line from ESC? Diversity is king in embedded! The mix of software tools, OS, board, chip, microcontroller and EDA companies still offers an interesting dynamic. I will definitely be back next year, but will be just as happy without Samson.

Before March Madness and the Final Four Butler win become too much of a distant memory, I wanted to briefly write about a different kind of “Final Four”, the four challenges which KH Kim, Executive Vice President, Samsung Electronics, Co., Ltd., presented at day three of the recent Synopsys Users Group (SNUG). The audience was in for a treat, the presentation was great in structure, content and delivery!

First, KH Kim was setting up the challenges using great examples from his ASIC view of the world. Worldwide consumer electronics sales was growing by 13% in 2010 and projected 10% in 2011 driven by smart phones, TVs and PCs, Apps are a major trend for all devices in video, gaming and business. The mobile Internet together with “apps everywhere” is accelerating smartphone adoption, which in exchange becomes the connective hub with other devices & services. TVs are becoming the hub for home entertainment, integrating gaming, internet, and video services. An finally, ubiquitous connectivity and consumers’ demand for 24×7 connectivity leads to a cloud and web-centric world. All this led to the set of graphs shown in the first picture I took here, summarizing the implications for SoC Design. Processing – the combination of CPU performance and GPU performance – Samsung sees growing by a factor of 50 from 2010 to 2012, while bandwidth requirements, the combination of memory and network bandwidth is growing by a factor of 250!

From this daunting prediction, KH Kim went on to articulate the “Final Four” Challenges in SoC Design:

• High Performance with Low Power
• Given challenges to CPU Performance and GPU Performance, SoCs can only be kept within Low Power budgets using Multicore CPUs (of course only shifting the challenges into programming), Multicore GPUs, low power design taking into account application scenarios and HPMG processes enabling transistor scaling.
• High Bandwidth
• The bandwidth challenges on memories and networks can be addressed by increasing 4G network bandwidth, the switch to serial interfaces to avoid signal skew and cross talk and Through Silicon Via (TSV) increasing electrical performance and overall memory bandwidth
• Design Complexity
• According to Samsung new features & functions have increased the IP count by more than 22x from 90nm to 28nm, gate counts have increased by more than 16x, while the chip size only doubled. As solution, process migration becomes a must to deal with the increase of chip sizes and 3D ICs with TSV seem unavoidable.
• Short Turnaround Time (TAT)
• Well, the rate of growth in design productivity is still much lower than Moore’s law resulting in increasing design times, while product life-cycles are shortening over time, which demands fast design TAT. The only way to deal with that are the use of IP,which Samsung sees evolving into sub-systems of discrete IP blocks connected through busses doing computation and communication. Software is overtaking the hardware effort and the trend toward multi-core designs further complicates software development & debug. Samsung sees Platform Based Design as a key requirement, for which virtual prototyping has emerged to enable early (pre-silicon) software development. Finally, Samsung sees ESL (Electronic System Level) design being at the early stage of adoption to close the design productivity gap!

As a system-level guy I am of course very much excited about Samsung adopting and pointing out system-level design as key solution to the fourth challenge.

High degrees of automation in architecture design, high-level synthesis, transaction-level modeling and virtual prototyping become key for faster TAT, higher Quality of Results (QoR) and earlier software development.

The photo I took of the appropriate slide is shown on the left … and the arrow used here  is very akin to the graph I used in the first blog post I ever wrote. System-level design has reached the foundries! It is not alone, but recognized as one of the key solutions to the four main challenges.

The road was long … but we are getting there!

In  gearing up towards the Synopsys Synposium – our very first own virtual conference – I am thinking back to all the types of virtualization I am using myself. I am wondering how right Billy Joy was in his famous Wired Article “The Future Doesn’t Need Us”. Well, we have a long time to go, I think, and we as humans are not quite yet an endangered species, at least for a while.

So what types of virtualization was I involved in recently? Well, there is a bunch:

• In day to day life at work I am involved in providing virtual representations of hardware to software developers and hardware verification engineers. This type of virtualization allows to work with a representation of the hardware a long time before the hardware is actually available. It provided real time to market savings.
• We are re-modeling our house. With Google Sketchup we are using a full 3D model of the house to decide on how to decorate (see the upper left picture). Two effects kick in here. First, the world really is flat. It would have taken me a couple of weekends to become fully proficient on Google Sketchup’s modeling capabilities. It did cost me less than $200 to virtually hire a firm to provide me a fully functional, accurate model of the house within a couple of days. There are plenty of firms worldwide providing Google Sketchup services. The second effect is one of time and cost savings. Pre-viewing things virtually in the virtual house allow us to make decisions faster and to get highest quality at the end – we are avoiding surprises at the very end when for example the cabinetry is built.
• I am using Facebook and LinkedIn pretty regularly. It allows me to keep – virtually – in touch with friends and colleagues.
• I have run several virtual trade shows now – we started last year. They allow to reduce cost on all side. Vendors reduce show preparation and execution cost, attendees reduce travel time and cost and can be very selective in what they look at. The next virtual show we will be doing here at Synopsys is the Synposium from August 31st to September 2nd.

So, why am I optimistic that the future will need us after all? Well, with all virtualization the human element still remains at the core. All virtualization technologies reduce cost, time to results, improve the quality of the end result and make the interaction more efficient. But all the actual content comes from us – humans – and will come from us for quite some time. Even in a virtual tradeshow the most value can be achieved by actively interacting with the vendors present for instant messaging like communication. While Billy Joy argues successfully in “The Future Doesn’t Need Us” how robotics, genetic engineering, and nanotech are threatening to make humans an endangered species, I don’t think virtualization is contributing to this trend given that it just makes interaction more efficient. But then again, I may be wrong. Let me know what you think!

So see you next – virtually – at the Synposium, a Synopsys Virtual Event, to chat about the benefits of virtualization at our virtual system-level design booth. In addition, the virtual show will allow you to learn from the comfort of your desk about Synopsys EDA software, IP, prototyping and services used in semiconductor design, verification and manufacturing. Until then I am off doing non-virtual activities during my honeymoon

Writing this Blog post feels like being Sally Bowles in the musical Cabaret when she sings "Maybe This Time". Since at least ten years the industry has been looking at the annual Design Automation Conference (DAC) and thought it would be the beginning of an era of system design, only to then realize next DAC around that most system-level design technologies have not yet crossed the chasm. Something feels different this year around. Here are my top five reasons why this is the year of system-level design, in a Letterman count down style:

FIve: Technology consolidation has begun. Well, it has accelerated. What has happened over the last year is that Synopsys bought CoWare, VaST and Synfora – enhancing their technology arsenal for for algorithm design, ASIP processor design, high-level synthesis, architecture design and virtual prototyping. Cadence has bought Denali – trying to catch up somewhat to Synopsys’s position in IP. The way we look at system-level design involving Systems on Chip and Chips in Systems is fairly straightforward. Users need lots of blocks in their designs. They need to either be able to re-use them or make new onesfast. They then need to integrate them into one or multiple chips in the system, assess whether their connections are properly architected and provide prototypes of them as early as possible to provide links to embedded software development. This results in needs for IP and various views of it (including system-level models), needs for technology to create new and differentiating blocks fast, to efficiently integrate blocks and finally to provide prototypes for software development. With the accelerated consolidation of technologies it becomes easier to optimize flows across different technologies. See us at the Synopsys System-Level Booth to check out the technologies we have in this domain.

Four: Design Chain enablement becomes a key requirement. Pressure for enablement across the design chain has increased tremendously. In the chain from semiconductor IP providers, to semiconductor providers, to system houses and finally software developers we increasingly see the respective next element of the chain driving the previous one in supplying the right models. A great example are virtual platforms, which allow system houses and semiconductor providers to more efficiently interact. See our suite demos on virtual platforms to find out more.

Three: Standards enable interoperability. The standards-enabled ecosystem (see picture on the left) has grown tremendously since last year. Standards like Accellera’s IP-XACT and OSCI/IEEE SystemC TLM-2.0 enable a strong ecosystem which allows to make sure that system-level technologies can interoperate properly, allowing users to create repeatable flows. Check out our partners at the Synopsys Standards booth to see how SystemC TLM_2.0 enables interoperability.

Two: Links to Verification find adoption. Being on the move to higher levels of abstraction is now combined with strong links back into verification. A fair portion of the system-level design market has been “ESL Verification” for a while, i.e. connecting transaction-level models to verification. Over the last year we did see the trend continuing and more and more developers now make software part of their testbenches for hardware verification. Check out the paper we co-authored with Infineon called “High Speed Models for Automotive Microcontrollers: Verification of the TriCore AUDO FUTURE TC1797 Virtual Prototype”.

One: Foundries are starting to incorporate system-level flows. Not only links to verification but even links into semiconductor technology data find their adoption. Performance, Power and Area (PPA) data characterized at various technology nodes can now be made available to drive decisions at the system-level. For example, in the TSMC system-level reference flow we recently announced, users can see with data created using virtual platforms at the transaction-level how the software will impact power consumption at different technology nodes. Check out our system-level reference flow at the TSMC booth.

Time will tell when and how system-level design technologies will cross the chasm and find mainstream adoption, but in a Sally Bowles “Maybe This Time” fashion it certainly feels different this time around. See you in Anaheim!

The Barcelona sun finally starts to arrive and helps to put the serious business being conducted here into a supportive environment. The best deals are being cut at the outside coffee table. The forward looking roadmap conversations happen by sitting together on the fountain walls.

Mobile is a massive business. Indian software services company WIPRO employs about 1,100 engineers in the mobile practice software services alone. As their general manager Arvind Jayabal points out they prefer doing their work in the fully green oriented WIPRO facilities rather than being forced to work at their international customers facilities. One forcing function for that is the infrastructure to develop software, like specific development board, which may only be available in limited quantities and locations. Virtualization of electronic platforms should be able to solve this problem soon.

Not less massive – from a booth perspective – is the appearance of Microsoft’s new Windows Mobile OS. Even on day 3 a faithful crowd of visitors listen to what the moderator has to say about the great features of managing your social life. You can aggregate all of your friend’s data from your own address book, calendar and FaceBook. Looks very cool. Many people are listening to this while happily typing an e-mail on their Blackberry or checking FaceBook on their iPhones….

Mobile video remains an interesting topic throughout the show. CEVA showcases their newest flagship, dual core DSP. The two DSPs are actually performing different tasks within video processing and have been optimized for those using the latest processor design technologies in this area. The CEVA CTO, Erez Barniv, points out proudly that a full rate 1080p HD video can run on an FPGA implementation of their DSP at just 50 MHz clock speed. This provides a promising outlook to using this new core for actual handset chips. DSP industry analyst Will Strauss stops at the demo and is significantly impressed by the technology as well.

Cambridge based mobile IP leader ARM is presenting several netbook products in their booth. More and more of their Chinese customers require them to predict performance for a specific set of target product constraints. ARM is addressing this through their sophisticated traffic generation tools combined with their partners providing the exploration and modeling technologies for ARM’s interconnects. They also point out that significant breakthroughs on the software side are necessary to keep their Santa Clara competitor on a distance in their home market. “They told us, before you can do Flash, you can’t sell real computers. Now we have it. What is their next challenge?”

The green topic in terms of power consumption continues in the infrastructure market. If you are dialing 911 from your cell phone in the US your location information should better be true. TruePosition is the provider of pizza box sized electronics that AT&T and T-Mobile are putting on their basestation towers to calculate your position from relaying several basestation measurement data. Many of these types of infrastructure systems are today being implemented using a combination of FPGAs and DSPs. The race for getting all the ‘green content’ is on between the TI and Freescale and Xilinx and Altera. In the end only the innovation of the system OEMs to advanced algorithms, software implementation, hardware implementation or custom processor design is making the green difference. The semiconductor companies just deliver the basic ingredients.

Away from the business discussion into the consumer view again one booth caught a significant attention, mostly because of clever marketing. The booth for “Powermat” was entire closed with the exception of a small entrance where customer had to line up for badge scanning. The process was deliberately slow, so a busy line would form. The product concept? Put your Smartphone into an additional protection sleeve that contains a power plug and a wireless charging device. Carry around a much bulkier phone all day so that when you come home you can just drop it on the Powermat, where it charges. Spend lots of dollars on ‘new sleeves’ for each of your device and discard the included charged from your device. If they can stay in business until the phone manufacturers will include the technology into the standard phone package this maybe interesting.

In the end business managers return satisfied from the show. It is a worthwhile concentration of decision makers in the industry. They have their calendars marked for 2011 already.

Orientation on the second day is a lot easier. Enter hall 8 where the titans of the industry play. Make a right at docomo, go straight to Research in Motion and head straight into leader Nokia? Hold on, Nokia was not exhibiting this year at the event! They offered a comfortable Rikscha ride from the Fira to their meeting place. Even though they refrained from the race to show new hardware, they made a significant software announcement with Intel to merge their Linux efforts into one. This again underpins Intel being serious about their Atom strategy for the mobile market.

So what was the stretch in this day? It was the low-end to high-end stretch. On the high end you would find small software players such as a Swedish company, Ikivo, specializing in high performance user interfaces for selecting from your address book or list of songs. Or specialized IP companies like Chips & Media from Korea producing high performance video IP. Of course the big semiconductor companies play in the performance game, such as TI with their OMAP processors. You wouldn’t expect that this processing power is actually needed to drive something as simple looking as an eBook reader, where the display update speed for the sophisticated low power displays is heavily influenced by the digital signal processing done by the processor. What do all of these examples have in common? It’s the combination of performance of software and hardware. It is critical for this industry to optimize both. Many times it can be done using virtualization technologies sometimes it will require additional subjective testing for the final selection as well.

On the low-end Vodafone announced the $20 retail phone (note – this is without subsidies). Customers can do voice and SMS with it. Imagine the amount of hardware optimization that will produce silicon at that cost level. Not only phones need to be extremely cheap to serve the underdeveloped areas, the network infrastructure needs to very affordable as well. Indian developer VNL demonstrated the low cost, rural area GSM infrastructure, which is using solar powered repeaters to get the GSM signal out into the country side. They are able to provide network operators with revenue even at ARPU of $2. Here the simulation of the physical layer for GSM is critical as it determines how far the operator can stretch the equipment. The chairman of the company told me that a local team of construction people can put the battery, solar and antenna on a roof top in just under 4 hours.

If you think the hardware and software content solely drive the technology edge, Samsung proves that you are mistaken. Their ‘Wave’ phone displays the brightest color with the lowest reflection and the easiest touch in the industry. It doesn’t look like they will license their ‘super-AMOLED’ technology anytime soon to their Cupertino based Smartphone competitor.