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A View from the Top: A System-Level Blog
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    A View From The Top is a Blog dedicated to System-Level Design and Embedded Software.
  • About the Author

    Achim Nohl Achim Nohl is a solution architect at Synopsys, responsible for virtual prototypes in context of software development and verification. Achim holds a diploma degree in Electrical Engineering from the Institute for Integrated Signal Processing Systems at the Aachen University of Technology, Germany. Before joining Synopsys, Achim has been working in various engineering and marketing roles for LISATek and CoWare.

As Time Goes By

Posted by frank schirrmeister on February 2nd, 2010

Looks like I almost didn’t get to my yearly review of what happened ten years ago in the technology outlook section of IEEE Spectrum. Well, I could blame it on the fact that apparently the January 2000 section of the technology outlook section did not survive my last garage cleanup. But thanks to digital distribution I could find the appropriate issue to compare where we stand 10 years later.

image The Technology Outlook section kicks off in the IEEE Spectrum of January 2000 authored by Linda Geppert and William Sweet with a discussion of the importance of standards. Microsoft was on trial for “proprietary standards”. Billy Joy was interviewed about JAVA, put into the public domain by Sun even though they controlled modifications and extensions to “protect it from the fate of SPICE and Unix”. Leonardo Chiariglione talks about what good has come from proprietary standards even though he also drove MPEG-2 as a standard.

So what was up in EDA? Of course! It was all about standards … The feud between SystemC and SystemVerilog was in full swing. Today, with 20-20 hindsight, we know that Co-Design Automation just elegantly played a MBA text book strategy game – picking a strong opponent to beat up – even though the technical differences between SystemVerilog and SystemC were pretty clear from the beginning. Now we also know that it worked.

Linda’s article kicks off with the three obstacles for IC Designers – lack of a unifying language for hardware and software, verification of design correctness and timing closure.

Focusing on the first here, Co-Design Automation is mentioned to have “ruled out the usefulness of extending an existing language to meet system-on-chip needs”, with candidates for extension having been C, C++, Java, and Verilog. Satisfying the three requirements which they set forth for a new language – unification the design process, improvement of design efficiency and evolution from an existing methodology – SuperLog was conceived. The opponent they had chosen was the SystemC Initiative. Several partners, including Synopsys and CoWare, believed that no new language was needed. They introduced SystemC, a modeling platform that extended the capabilities and advantages of C++ into the hardware domain. The supporters of SystemC came top down so to speak and violating Co-Design’s third rule to be evolutionary. They based their path on the observation that most software developers use C and C++ and many systems developers use C++ already to describe their systems at a behavioral level. But until SystemC it has not been possible to describe hardware using the same language.

So where are we ten years later? No surprise – standards have taken over. And has anybody won? No, both have, in their own way. Co-Design Automation was acquired by Synopsys and SuperLog was put into the standardization process to create SystemVerilog for both verification and design. This was the start of the end of proprietary languages like Verisity’s E. Today SystemVerilog is the clear winning language for evolutionary improving existing hardware design and verification – just as Co-Design Automation had predicted. Has it found an entry into software development? No, it hasn’t.

Equally, on the software side, SystemC has won the battle when it comes to becoming the interconnect fabric for virtual platforms, which enable software development. Standardization played a similarly important role. Synopsys acquired Virtio, put key technologies into OSCI and the TLM-2.0 APIs were born from here as a collaboration within the standards body.

So what is the conclusion 10 years later? Well, three things. First, I have to give it to Steve Leibson and his law that it ‘takes 10 years for any disruptive technology to become pervasive in the design community". It looks like SystemC and SystemVerilog are two good examples of his empirical observation, then formulated as “law”. Second, standardization was and is a key component for technology adoption. And third, business is just business and often trumps technology. Co-Design Automation’s approach ten years ago to pick an opponent to get attention as a small company (even though technically the languages were obviously quite different and for different purposes) was the right business approach and played out beautifully, almost like in MBA text books.

Off to a new decade … It remains interesting!

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2 Responses to “As Time Goes By”

  1. Dave Kelf says:

    Hi Frank,
    Nicely put! I think it is fair to say, especially with hindsight as you note, that SystemC did have its evolutionary path – for the folks using ISS processor models and wanting to add hardware accelerators, so software guys could easily compile the lot together. It’s great for this. The problem was that this initial idea (along with a useful verification angle) got overblown into a language for all purposes and then, a bit like Esparanto, it became a really easy target as there was no high value focus. I guess the fourth rule should be focus on the sweet spot application. Maybe a general rule for ESS! Anyway – enjoyed the article as I do your blog in general. Thanks. Dave

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  2. Darren Galpin says:

    This was the start of the end of proprietary languages like Verisity’s E. Today SystemVerilog is the clear winning language for evolutionary improving existing hardware design and verification

    Um, really? Given that e is now on the third standardisation round with the IEEE, having been a standard since 2006, it was hardly the end of the language, especially given the amount of users still out there – you can follow the progress of the IEEE working group for e on the official website. I’m the chair of the working group, and also a user of the language. I’m not affiliated with Cadence in any way, just so that you can see it isn’t run by and for any one company.

    The language isn’t dying out either, with more and more users out there, with a number of new blogs on the language (see this link for a list of blogs and the like. This fixation with SystemVerilog also misses the point that there are a very large number of users out there who use VHDL, and consequently have a large amount of legacy code to support. Given the issues involved in co-simulating VHDL and SystemVerilog, there isn’t a huge incentive to move over either. It makes sense if you are a Verilog user to migrate, as you gain many features (some of which have been in VHDL for years…), but it isn’t the “clear winning language for evolutionary improving existing hardware design and verification”. It’s three languages glued together in one kernel…….

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