Archive for July, 2009

Rajesh Gupta UCSD put it in clear words: “Low power design for complex chips is a solved issue. Designers have tools and methodologies and getting their job done.”  Game over?

Not really, as debated by the panelists during the Design Automation Conference panel on “From Milliwatts to Megawatts”.  While some of the panelists were still hanging on to do better RTL implementation – albeit making use of more sophisticated approaches with high level synthesis – Nokia and IBM had a much different perspective. Power is a system issue and much of it is determined in how the software stack enables the user to get the most value from the application within the power budget.

On one end of the spectrum is getting the best response time in a data center running expensive Oracle software. Shutting down as many servers as possible within the performance requirements is the answer according to the IBM fellow.

One the other end is managing a smart phone running running out of juice while navigating using Google maps.  Does the phone shut down the music player automatically or does it give the user an option to chose how long the battery will still last; the challenge presented by the Nokia Berkeley research lead.

The architectures to deliver on low power will vary a lot. Essential is that only a systemic view using the software application use cases provides the answer for defining the system architecture and the power management strategy implemented in software. The answer is Electronic System Virtualization, not behavioral hardware synthesis.

Will the 47th DAC next year have a panel on real cases of power optimization at the software level?

Just as the Design Automation Conference in San Francisco comes to a close some cynics are pointing out that once again this was the DAC of ESL and we probably can look forward to another one like that next year in Anaheim . This feels like the proverbial road trip during which you hear from the back seat every five minutes “Are we there yet?”. There certainly were interesting panels and events at DAC, like the System Prototyping panel yesterday, for which Rick Nelson wrote a good write up here.

Personally I attended the 7th Annual ESL Symposium Luncheon sponsored by Mentor Graphics and moderated by Wally Rhines. The panelists included Nitin Chawla from ST, Joachim Kunkel from Synopsys, David Black from ExtremeEDA and Wolfgang Rosenstiehl from the University of Tuebingen and Alan Su from GUC.

As always Wally had lots of data. While he likened ESL at the beginning to technologies which took 30 years to adopt, he then showed graphics like the one on the left  confirming actual market growth. He called ESL one of two technologies leading growth in EDA. According to Mentor’s surveys, ESL adoption is driven by design complexity, verification challenges, design challenges to meet power and performance requirements and time to market demands.  When it came to the panelists, Joachim Kunkel and Alan Su focused in their introductions on system prototyping while the other panelists were more focused on high-level synthesis.

At one point the panelists had gone down the route of ESL synthesis so far that Daniel Gajski stood up and asked the panel whether ESL is only high level synthesis or whether there is more to it. The panelists attempted answers, mixing in verification, but in my mind one key question was left unanswered: Where does a block and where does a system start? What is the “S” in ESL?

Unfortunately the discussion seemed at times to miss the separation of block development and block integration. High-level synthesis is today well applicable for block development. However, with block re-use in hardware reaching 70% and 80% levels, the other challenge in the design process has become the integration of blocks, re-used or newly created. Several questions later-on confirmed this lack of clarity as the question “how far away are we from synthesizing complete chips” came up in several variations.

Overall, however, I am glad that according to the data ESL is growing and has not been voted of the EDA island … Off to the next round and let’s hope that we are progressing even further until we meet in Anaheim next year.

Today the problem for companies developing electronic systems is not anymore the existence of the right technology, but rather how will I deploy it. Electronic System Virtualization must cover areas such as processor design, system architecture, oftware development, go-to-market enablement, configuration, etc. The virtualization of the electronic system must start from the specification all the way to the deployment of the system itself independently of the system being a core, an SoC, a board, a device or a network of devices.

The use of electronic system virtualization is proven to deliver the value. Many companies are now presenting their results and the significant benefit they are getting. However none of these companies have considered a single use case for virtual platforms for example. They have derived results from using virtual platform as an infrastructure across several of the product life cycle tasks. 

The implication of this reality is that the deployment of Electronic System Virtualization technologies will require individuals and organizations driving their deployment. It will require executive support, it will require the willingness to introduce changes.

The drivers behind this change will be the leaders of tomorrow.

For those tracking the history of the last 10 years of DAC panel discussions about ESL, they fall largely into two camps: the language debate and the high level synthesis debate. The 46th DAC was no exception to that pattern, and frankly, it is getting very old…

On the language debate you will find the debaters who think that by just changing the language, that designers use, to be something that resembles C or C++ , productivity will go up dramatically.  Some people will believe just because it is C/C++ they are closer to have a cheap, open source based tool flow.  The reality is that none of these statements are helpful or practical for real design life. A language in itself has no value without semantics and tools that exploit the semantics for a purpose (also known as a use case).  Open source approaches for tools are the last thing design teams want to rely on for their critical design project during a recession time.

On the high-level synthesis it is simply the question if the higher abstraction level for hardware block design is the critical problem for multi-core SoC design. With the cost of software development skyrocketing for fabless and integrated semiconductor companies, how much do they really want to invest into the hardware component design automation. Is it more important to make 100 hardware designers productive or 400 software developers?

It is time to concentrate efforts on the real big cost savers for multi-core design. Rather then spending the time on making that one new RTL block easier to develop, spend the time to prepare the models for the many other IP blocks on the chip, that are critical for architecture exploration and early software development.

It is time for Electronic System Virtualization. The 47th DAC will have to demonstrate, that it can concentrate its attention on the bigger issues.  Who wants to sit through another ESL debate next year?

Qualcomm reporting on the opportunities and challenges of Virtual Platforms for their system designs. QC has been highlighting the productivity gain they get from Virtual Platforms for Software Development, Architecture Definition, Hardware Development and Early Customer Success. Qualcomm is following an incremental Virtual Platform creation approach to incrementally enable software development and get value out of VPs as early as possible. QC has reported a significant quality gain because they are able to develop the tests upfront and do not need to wait until the HW is available for the test development. VPs help QC to improve the coverage of their testing using complex software use-caes. VPs have enabled QC to create tests that they could not create before. Challenges remain on the Virtual Platform enablement side. For QC it was key to choose a standards-based modeling language and TLM to ensure interoperability between models. The driver to select a tool and/or language is its ability to create virtual platform models that are fast, at a higher level of abstraction, are interoperable, and that can be created in an easy way. QC reported that it is key for them that their engineers are enabled to carry out the modeling. It is of significant importance that a wider set of engineers/IP architects are enabled to create models with the above mentioned characteristics.

The Tuesday’s panel “System Prototypes: Virtual, Hardware or Hybrid” at DAC was well attended with an active and exciting discussion among the panelists and the audience. Panelists came from Amicus Wireless, Qualcomm, LSI, Synopsys, ST-Ericsson and CoWare. There was a consensus that there is no on-size-fits all solution for prototyping. Different design tasks such as system level architecture definition, software prototyping and bring up and implementation prototyping have different requirements on the prototyping solution. Qualcomm and ST-Ericsson have reported about their successful adoption of virtual prototyping using Virtual Platforms for early software development. Both reported that Virtual Platforms has significantly smoothed their software bring-up step-function that they typically had without Virtual Platforms and when the hardware became available late in the design. Questions have been raised about the accuracy of Virtual Platforms. Here, the panelists where in agreement that a Virtual Platform does need to provide the accuracy required for the different design tasks such as being just functional accurate for software development. I have been reporting a trend that we see at our Electronic System Virtualization solution users moving away from spreadsheets for the architecture definition. This was hitting a question from  the audience how Virtual Platforms can be used for HW/SW partitioning. System level architecture prototyping is done using non-functional workload models characterizing traffic scenarios for application/task mapping as well as interconnect and memory subsystem optimization. This way the dynamics of a system can be captured which is not possible using static spreadsheets. Other questions were about using Virtual Platforms after silicon is out. Here, the Google Android Emulator was mentioned as a perfect example how Virtual Platforms deliver value to even the application software developers by having access to a fully virtualized environment including GPS, Internet, Accelerometer to develop disruptive applications. People in the audience where also reporting about the trouble they face when trying to bring up systems on an FPGA, it simply does not fit for many cases. FPGAs are used for block level implementation prototyping but cannot provide a full environment. It was an exciting panel and it has clearly shown the increasing demand and adoption of Virtual Platforms in the industry.

The votes were cast, THANK YOU for your votes to all of us EDA Bloggers and CONGRATULATIONS to Karen Bartleson for winning  the “NEXT EDA BLOGGER” contest.

Other than the Denali party I saw lots of system-design activity at DAC. In the panel on System Prototyping the panelists were remarkably aligned with emphasizing the need for both virtual and physical prototypes, which connected via SCE-MI can become even more powerful. Another panel on the ecosystem featured ARM, Cadence, Virtutech and ST and dealt with questions like :Where do these models come from” (Aligned answer The IP provider, please).

Today will be my personal last day at DAC for this year. I will present ways to increase verification productivity at 3pm at the DAC Exhibitor Forum. My colleague Filip Thoen will show Synopsys SuperSpeed USB 3.0 virtual platforms at the DAC Virtual Platform Workshop (sign-up required). In addition the Standards booth will be in full swing again, today featuring Greensocs at 9:00am, Forte at 11:00am, ARM at 1:00pm and Target Compiler at 3:00pm.

See you on the show floor!

This week CoWare has been pleased to welcome Victor Leonov, distinguished member of technical staff, Motorola Mobile Devices and user of CoWare Platform Architect, to the CoWare DAC booth as a expert guest speaker on architecture design. His presentation, Achieving Optimal Cost-performance Balance in Advanced Wireless Modem Chipsets using Stochastic Simulation, was of high interest to SoC system architects and project managers here at the show.

Motorola uses CoWare’s ESV environment to analyze system architecture and optimize system performance of the next generation wireless modem chipset for Motorola mobile phones. The key design challenge during product planning was to confirm, as early as possible, that a single modem SoC was able to support the performance requirements of a complete portfolio of handsets, without overdesigning the modem SoC. The results of the project are impressive:

• Motorola’s chipset architecture was optimized to meet all product tiers’ corner use cases
• It’s product architecture fits into three groups of performance-critical HW configurations
• Each configuration meets targeted product cost
• Final product exceeds targeted performance by approximately 10%

Visit the booth Wednesday morning at 11am for more details!

 How many time have I heard now that software is the growing problem, that software is the savior for the traditional EDA companies, that the software teams are out growing the hardware team, yet the software tools budget are not, …

This week design automation conference is no different; you can hear it from the CEO of the EDA companies to their soldiers, from the executive of semiconductor companies to their soldiers, from the analyst to the press, to even the taxi driver in San Francisco. Software is the problem; we need to do something about it!

But yet when it comes to doing something very little of these players are effectively executing on it. Everything is very much about RTL, optimization of the hardware, etc. The true software solutions are few. The first thing we hear from customers is “yes it is about the software, but what about my hardware problem”. The second is from the companies (trying to protect their legacy) “yes, software is the problem, but let me explain to you how what I have today solves the problem”

Well let’s be realistic, if what exists today from these companies and what is being used by the engineers was solving the problem, then there would be no problem!

Addressing the software problem requires the willingness to change. To change the development process, to retool, to be willing to say I want to invest in these new technologies, to be willing to look at the product life cycle management, to stand up and say “Yes there is a software problem and I will not wait for the storm to pass before I fix it”, “Yes there is a software problem and I will lead my organization to make this difficult but necessary change”.

Are you this engineer, this manager, this executive that will say yes and drive the change? If not get out of the way, the wave is coming anyway.

Well, on Gary Smith’s “What To See at DAC” list 16  out of 24 recommendations start with ESL. The most thoughtful comment I heard on ESL during yesterday’s DAC was related to ESL, but made me think. John Aynsley of Doulos said during the”Town Hall” meeting that he had thought that this years DAC would be the DAC of high-level verification, but it seems it is the DAC of high-level synthesis. Well, the two very likely are related. The drive towards higher levels of abstraction always had been driven by a combination of faster implementation and more productive verification – assuming you can be more productive “up there” and then minimize the verification overall as I outlined in a recent column called “When one plus one needs to be less than one”.

Most of the day I was actually tied up in customer meetings. I heard good things about our System Prototyping Luncheon with LSI and Intel as customer presenters with more than 100 attendees. In our System-Level Catalyst area at the Standards Booth we had standing room presentation (see picture) and demos. So users are definitely interested in understanding ESL technologies.

I briefly attended the town hall meeting at the SystemC North America User Group. They employed interesting technology with which the audience could immediately vote on questions of interest (TED alert – in Germany 15 years ago we had this thing called TED for which you could call in a vote … sometimes with interesting results ).

Results were sometimes interesting albeit not always surprising. 90% of attendees liked an open source reference simulator implementation. The majority of attendees seemed to use SystemC for modeling at the Loosely TImed level of abstraction. An automatic path to implementation was the most requested “What does SystemC need”.

At DAC today? There is GreenSocs Breakfast Panel titled: “SystemC TLM: Just add water?” at 8:30 am. You can expect lively discussions when Synopsys’ Andrew Dauman participates in the panel “System Prototypes:Virtual, Hardware or Hybrid?” at 10:30 am and Joachim Kunkel discusses “Silicon IP – Beyond Chips to System” at 3:30 pm. At our Standard’s booth we will have today the following schedule:

See you on the show floor!