Archive for February, 2009

 

During my last garage cleanup I got rid of most of all the paper copies of my IEEE magazines. The only surviving ones were the IEEE Spectrum January issues, which typically were the analysis and forecast issue for the upcoming year. Since then every January I am reviewing the IEEE spectrum forecast issue from 10 years ago to see how good or bad the predictions actually were. That is quite a fun exercise!

The 1999 IEEE Spectrum January issue shows Superman Clark Kent ripping off his suit and trying to decide whether to use the telephone or Internet booth to change his clothing. The telephone booth shows a classical US telephone, while the Internet booth shows a device with a keyboard screen and a headset attached to it. The underlying text calls out “Internet Technologies” as new challenges and opportunities.

Well, it looks like they got this one right given that at home I am now frequently using Skype connecting to my parents in Germany via video phone, my employer Synopsys is using a VOIP phone network and in general we are facing consolidation in the telecommunication industry. In reviewing the table of contents, electronic design automation had its own section written by Beth Martin. Well, that’s good news, a couple of years later I believe this section dropped from the forecast issue. When checking out the section in more detail, the marked highlights were:

• Design moves to a higher level of abstraction
• Design reuse ramps up slowly
• Hardware, software join hands early on
• EDA casts a wide business net

Oh well, 10 years ago we were already talking about higher levels of abstraction and hardware / software co-design. Has it really been that long? In one of the paragraphs at that time executive officer of LSI Logic Corporation, Wilf Corrigan, was quoted that the most pressing need for new EDA tools is a better methodology “to allow software developers to begin software verification more near the same time that chip developers begin to verify the hardware”. So the pressure was there 10 years ago already. The article later claims that the tools of that time were still in their infancy and that users can “presently do hardware software partitioning to prevent design problems that might occur downstream”, but that “the tools available at the time were inadequate, the technology was immature and poorly integrated with tools and methodologies at the RTL level and below.”

It is good to see that we have made significant progress since then, even though it took 10 years. Today’s virtual platforms for example are well-connected with verification flows for RTL, increasingly becoming the entry point for hardware software verification in the design flow.

Given that hardware and software are growing closer together the other interesting portion of the IEEE Spectrum technology forecast issue of 1999 is the software engineering section. Interesting enough, while the EDA section was outlining interfaces to the software world, the software engineering section initially does not talk about hardware and all. The mentioned highlights are:

• Sun battles to keep control of Java
• Jini offers magical networking solutions
• Web standards need support
• The world waits for the year 2000

Ah, I forgot. There was the Y2K doom’s day preparation going on at full swing in 1999. When reading the articulate in more detail, I must revise my original thought that hardware wasn’t mentioned, because the article clearly points out different attempts like Jini to become independent from the hardware on which the software is running on. Operation Systems like Solaris, Mac and Windows (no Linux mentioned!) provided the abstraction layers to let the software be independent from the hardware. Jini at the time was seen as a way of discovering what services are available to applications and the network and how they could be accessed.

Still, the difficulties off debugging at the hardware/software interface are only mentioned when viewing the world from a hardware perspective. It is not clear to me, whether that has really changed over the last 10 years. Today most of the discussions and software engineering seem to be about application software development and even though dependencies on hardware have been steadily growing, the hardware software debug discussion still seems to be largely dominated by hardware engineers.

Overall though, I’m quite relieved that we seem to have made quite some progress since 1999. While the issues of hardware / software co-development, increased software productivity and better hardware / software debug were already visible in 1999, the pressure and need has been growing quite tremendously from there and led to quite some interesting technology developments. More broadly applicable virtual platforms are a great example, as they are used not only for embedded software development but also for verification. We still have some way to go though and are still living in interesting times!

Synopsys announced last Monday a breakthrough in verification, system validation and embedded software development technology. There was good coverage, for example in Ron Wilson’s and John Blyler’s blogs. One main question we got from users and the press was about how this all works together with the virtual platforms we provide as part of our Innovator environment.  John Blyler asked it flat out “One other question: How will this hardware prototyping platform eventually work with Synpopsys software (virtual) prototyping tool – from the Virtio acquisition?”

We have demonstrated interfaces to hardware based solutions for a while with Eve and Palladium. Synopsys now has the three necessary technology components for hybrid prototypes in house and are preparing for demonstrations with various customers. Starting on the hardware side, physical interfaces must be provided to connect the actual hardware prototype to the workstation running the simulation. PCI Express is a common solution here. Second, data must be transported using an agreed upon protocol between the software and hardware worlds. SCE-MI has become a standard in this domain. Finally, for conversion from the transaction-level model to the transport interface, transactors are necessary to translate high-level protocols like AXI, OCP and AMBA.

In addition we have talked to about 25 customers worldwide (yeah, I made it to be United 1K for the tenth year now) to understand their needs. We were able to condense the use models of virtual platforms and FPGA prototypes to five main use models:

• RTL Reuse and Architecture Verification: Given the high IP re-use rates in today’s design, RTL may exist from previous projects or may be acquired. While more and more IP users request high-level models as part of an IP purchase, it may not always be available. Hybrids of virtual platform and FPGA prototype allow a virtual platform to re-use existing RTL and avoid modeling effort of potentially complex IP blocks. Given that FPGA prototype execution is essentially cycle accurate, it also increases overall fidelity and allows to swap out the virtual model with RTL to verify that architecture decisions were correct.
• Accelerated Software Execution: Due to FPGA implementation optimization for algorithm execution and not processor implementation, software typically runs on workstations and virtual processor models faster than in FPGA prototypes. Hybrids of virtual platform and FPGA prototype with processor models on the workstation allow overall faster execution while maintaining accuracy of accelerators and peripherals.
• Virtual Platform as test bench for FPGA prototype: Given that verification often starts at the pre-RTL level for validation purposes, system-level development efforts can be re-used for the actual RTL verification. Hybrids of virtual platform and FPGA prototype with the virtual platform acting as testbench avoid duplicate efforts and enhances model re-use
• Joint system environment connections: For popular interfaces like USB and SATA virtual platforms already provide real-world and virtual I/O interfaces, for example connecting to physical USB devices. In addition a daughter cards in FPGA prototypes provide real world I/O with interfaces to real life streams like the wireless physical interfaces. Hybrids of virtual platform and FPGA prototype with real world I/O on both sides allow real world stimulus to be used where most appropriate.
• Virtual platform “Virtual ICE” connected to FPGA prototype: Re-use of the virtual development environment running in a virtual platform including for example disks, USB virtualization, visualization etc. allows better access to FPGA prototypes and decreases set-up time. Hybrids of virtual platform and FPGA prototype with the virtual platform executing the development environment avoid additional development efforts, allow the FPGA prototype to be kept remote and increase familiarity for software developers who often prefer to just see a keyboard and screen

Over the next couple of weeks and month we will be demonstrating this flow using Innovator virtual platforms connected to the ChipIT FPGA prototypes using the SCE-MI 2.0 interface.

If you are interested in more information or a demo please don’t hesitate to contact me directly or contact the system-level design team directly.

While some of you in the US may be scrambling to get your old Mickey Mouse antenna replaced for the switch over to HD-Digital TV, a group of companies owning a huge amount of spectrum is preparing to get you going with HD content on your mobile devices. The wireless operators around the world, the AT&Ts, Vodafones and Docomos, are working on putting the final touches on a new standard called LTE (Long Term Evolution), which will provide 100Mbit/s peak performance providing access to the internet at warp speed, even while travelling at 200 miles/hour in the Shinkansen train. Along with that goal for the standard, the base station providers and cell phone manufacturers have to reinvent their platforms. Simple scaling of the previous architectures does not work.
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Where does this new standard put the biggest pressure? It’s the semiconductor companies in the wireless space. They are redoing their architectures to deliver the scalability and much higher speeds as compared to the previous generation (HSPA), which is deployed in the market today. Even if you are not into wireless design, by taking a look at the required 5-10x performance delta gives you an idea of the design challenge (Peak data rate 100Mbps vs. 14 Mbps today, latency 5 ms vs. 50 ms today, broadcast data rate improvement 8x)
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What does it mean for the design? Most design teams would be tempted to design a lot more optimized signal processing hardware, but by the time they would be done with that, the standard will be moving towards LTE-Advanced (1Gbit/s peak rate). Also, the flexibility of the operation of LTE does not lend itself to fixed architecture. So, what should you expect to happen in these leading-edge design teams? They will use processors wherever possible. Standard cores, customizable cores and dedicated cores will be used to differentiate their architecture in terms of power and performance. This is multi-design at its finest and, of course, with a huge amount of design challenges for the performance optimization of the architecture and the software.
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Is this all worth it for the semiconductor industry? Well, the operators certainly believe so. According to ABI Research’s senior analyst Nadine Manjaro, “ABI Research believes that NTT will also deploy LTE in Japan in 2009. We forecast that by 2013 operators will spend over $8.6 billion on LTE base station infrastructure alone. For operators that have already deployed 3G networks, LTE will be a key CAPEX driver over the next five years.”
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Interested in the most challenging designs around the world? Then quickly learn about LTE!