Archive for June, 2008

During the technical keynote at the Freescale Technology Forum (FTF), Freescale’s CTO Lisa Su (or “Chief Geek” as she called herself) painted a vision of “Tomorrowland”. The “Jetson’s” lifestyle of connectivity and availability of pretty much everything on demand will be enabled by embedded intelligence using “behind the scenes” embedded systems. The key innovations to get us there will be hyper-integration, multiprocessing and software. Lisa Su called for a strong semiconductor and system-level ecosystem as the key enabler, stating that “we all have pieces of the puzzle” and need to collaborate.

FTF’s location Orlando seemed this June for me with my German roots to be like an uncomfortably hot assembly of amusement parks, hotels and conference centers loosely connected by swamps. Inspired by the theme parks Lisa Su opened her keynote with the music of “The Jetson’s” TV series. She cited as examples for a revolution in embedded intelligence RFID technology, OnStar and our beloved cell phones. These devices collect information, process it and connect with each other, often behind the scenes even without us knowing. With miniaturization she quite convincingly predicted 1000 embedded devices per person in 2015.

Lisa Su translated the effects of the three themes introduced by Rich Beyer the day before – “Going Green”, “Health and Safety” and “The Net Effect” – into “Sustainability”, “Wellness” and “The Invisible Network”. Required sustainability of distributed renewable energy sources will cause revolutionary changes in energy generation, its localization and distribution. Wellness will be enabled by “Telemedicine” allowing remote monitoring and even remote surgery. Explaining how the power of the network comes true especially when it is invisible, Lisa Su happily admitted how her Mom beat her to owning a Blackberry and now sometimes ignores her while checking email J She continued to paint a picture of the “Tomorrowland” amusement park in which we wirelessly can get information which rides have the shortest lines and which of our friends are also in the park without us knowing.

From my system-level perspective I was most interested in the key enablers mentioned during Lisa Su’s keynote. She called the first innovation “Hyper -integration”, which in her view needs to become an enabling technology at reasonable cost. With Hyper-integration systems are assembled from sensors, control and a combination of software and processors.

Multiprocessing was stated as the second key innovation. Starting from secure MP platforms like Freescale’s recently introduced QorIQ communications platform, Lisa Su foresees in 2015 massively parallel processing enabled by 22nm technology.

The third key enabling innovation – Software – could have been mentioned first. Lisa Su called for open APIs, OSs and interoperability enabling seamless integration of software and efficient re-compilation to different hardware platforms. Today’s run-time platforms will evolve into common software environments with code re-use. Concurrent development of hardware and software will be critical and the hiring of software expertise is today already one of the highest priorities.

In closing Lisa Su mentioned that the innovation and enablement for next generation electronics is “just at the beginning”. As successful example of incubation and innovation she pointed to Freescale’s ZigBee activities. A healthy ecosystem will be required to get us there, given that “we all have pieces of the puzzle”.

Not downplaying the importance which semiconductors play in all this, it was most impressive to me how consistently Freescale stressed the system-level aspects and collaboration issues. As an industry we cannot enable next generation electronics without substantial increases in design productivity using system-level methodologies, models and tools. And we will need to cover a broad spectrum here, from helping digital signal processing design teams to assess how their algorithms fit into systems to virtual platforms enabling collaboration between companies in the design chain ecosystem to more efficient software development and re-use.

We indeed do live in interesting times from a system-level perspective. I for one am happy to be here!

I am at the Freescale Technology Forum (FTF) here in Orlando this week, where we are demonstrating our virtual platform of Freescale’s i.MX31 application processor. Freescale’s CEO Rich Beyer kicked of the conference with a quite impressive display of demos and partnerships with the three themes “Going Green”, “Health and Safety” and “The Net Effect”. It was very clear how system-level aspects are crucial to Freescale’s success and in many instances that knowledge is shared between Freescale and key partners. Rich Beyer made it clear that software is just as important to their success as is the chip itself.

The first demo showed the adoption of wireless technologies in industrial automation. Wireless technology is mostly used for data transmission here – including video. My respect to the demonstrator, on whom the demo setup played a trick and caused him to have to re-synchronize his setup in what Rich called a diving catch in front of an audience of 100′s . Well done. In the area of health Freescale called a partner on stage, who demonstrated a belt for mobile EKG analysis using embedded processing based on the Coldfire technology.

My personal highlight was a demonstration of HDTV transmission using Long Term Evolution (LTE) next generation wireless by Tom Deitrich. He showed nicely how mobile communication evolves beyond voice services and how the 50x faster transmission rates of LTE can be used to carry video. The technology from Freescale will be ready in 2009 for field trials with deployment shortly thereafter. Tom cited power consumption and integration as the key differentiators.

Together with Sue Bostrom of Cisco, Rich Beyer then demonstrated (at 6:55am her time in California) the Cisco TelePresence system. This fit both the green and connected themes and Sue Bostrom mentioned how they have already saved $150M in travel cost and with that reduced Cisco’s carbon footprint with the equivalent of taking 8000 cars off the streets for a year.

Finally Lynelle McKay introduced with great fanfare as “path to multicore” Freescale’s QorIQ communication platform. The software aspects were crucial in this context and Lynelle especially pointed out how virtualization technology enabled their partners to do early software development.

In summary a quite impressive display of technology! The key take away for me was again that traditional chip providers like Freescale are going well beyond the chip now and need the software and system to work right for them to be successful. Collaboration with system partners is crucial and the technology to efficiently interact – for example by way of virtual platforms – is a key enabler of such collaboration.

On Wednesday Mentor hosted its 6th Annual ESL Symposium here at DAC. The panel gave a great overview of the ESL space. ESL Synthesis and Virtual Platforms for pre-silicon software development seemed to come out as the two areas of ESL with the most adoption so far.

Wally Rhines opened the panel and reminded the audience that this market has grown from $70M in 2000 to over $200M in 2007 according to EDAC data, i.e. data which the EDA vendors actually report. So, while we were not looking the market has actually grown to over $200M already.

According to survey data cited, 70% use high level synthesis and 23% use TLM based verification. The main drivers are (a) Design Complexity with 16% of designs using more than 3 processors, 11% having more than 21 clock domains and 22% more than 10MGates of logic and data path, (b) Verification with 60% of re-spins have functional causes, (c) low power and high performance and finally (d) time to market.

Wally added that originally the ESL investments were in modeling, system analysis for performance and virtual prototyping. Now ESL models can also be re-used in TLM verification and ESL synthesis. Low power was quoted by Wally as “probably the biggest driver”.

First panelist to present was Viraphol Chaiyakul, Senior Director of Engineering in the QCT SoC Platform group. He gave a snapshot of the ESL adoption at Qualcomm. They differentiate verification, analysis and design. In verification Qualcomm already uses TLM-based hardware functional verification, software driven verification and early software validation. Model sharing and reuse by way of standards is next – they will adopt SystemC TLM-2.0.

In analysis Qualcomm does a lot of non-functional, traffic based trade off analysis and estimation. Going forward they need tools to allow quantification and definition of model accuracy and fidelity. They also propose a meet-in-the middle approach for modeling combining characterization and estimation.

The design area today uses block synthesis and simulation platforms for hardware software co-development. The key challenges are to make the ESL models golden, to verify the ESL models and to measure the quality of results. Going forward they look for synthesizable and verifiable TLM-2.0 flows.

Next up on the panel they had Prakash Rashinkar, Director of Engineering at Rambus. He talked about performance analysis for memory technologies. He introduced memory as the bottleneck with the skyrocketing data rates for memory accesses combined with advanced access and protocol techniques. ESL performance models are used at Rambus to design and validate complex access protocols. Prakash also pointed to SystemC TLM-2.0 as an important step. In summary for Rambus ESL is a key step to unleash XDR performance, it supports top down design, which in turn is accelerating time to market and enables re-sue of test environment for verification. ESL is a must have technology for them.

Kaz Yoshinaga, Researcher at STARC, was up next and he pointed to interoperability issues of transactions between vendors and the resulting importance of standards. Based on OSCI and additional application standards STARC introduced a transaction-level modeling guide separating communication from computation including a refinement path from un-timed to timed models. They confirmed that the models can be imported into major system-level tools. Transaction-level design is a common ground for successful methodologies. The first edition of the STARC guide is available and will be upgraded to support TLM-2.0 in early 2009.

Nitin Chawla, Senior Member of Technical Staff at ST followed as the next panelist. He focused in ESL synthesis. In their SoCs the application engines like video codecs and wireless modems create most of the differentiation. They start with C/C++ models and use high level synthesis to automatically create the RTL which they validate using simulation technologies. Next generation sequential equivalence checking will increase confidence for them. Design productivity improvements can be 5x compared to RTL. Combined with high-level model reuse they can reach about 10x productivity improvements. He called for better memory analysis and trade-offs to be able to explore a bigger design space. ESL synthesis is reality for ST, have done a large number of production designs. Key benefits are productivity flexibility and improved QoR.

Final speaker was Bernard Candaele, department head of SoC, IC & EDA at Thales. He introduced their project focus on high complexity system developments like the Galileo satellite navigation systems. They have several candidate platforms and use early software execution on virtualized platforms. In addition they are using ESL synthesis in some of their designs. The next challenge will be the maturation of tools and links to verification. Bernard mentioned a debate between HDL designers and ESL engineers as the methodology shift has impact on the design population.

Bottom line ESL synthesis and virtual platforms, combined with some performance analysis were the main drivers outlined among the panelists. The following discussion was largely moderated by Wally. The biggest factors to drive towards ESL adoption cited were management of design complexity, productivity and time to market pressures. For Prakash at Rambus the ESL performance models enable education of customers and even sales support. SystemC was quoted as the biggest advancement in EDA to make ESL possible. All panelists confirmed that SystemC TLM-2.0 is an essential step and ready for adoption right now.

In summary this panel gave a good update on the different areas of ESL usage – it is here today! ST pointed out that in some of their divisions 90% of the new IP blocks are now designed with high-level synthesis! SystemC TLM-2.0 came out as the unquestioned next important step at the transaction level – both for hardware verification and virtual platforms enabling software development and verification. Key challenge going forward will be verification of ESL models themselves to make them golden.

OK, here we are again from DAC and topic of today is multicore. Sumit Gupta from Nvidia and I had some interesting discussions around it, both using Multicore for our tools and using our tools for multicore. A good example is the NVidia Cuda architecture as introduced by Chris from NVidia during Sunday’s General Chair’s Reception.

NVidia had indicated in Sunday’s presentation that the applications for GPU multicore architectures grow beyond just graphics and of course EDA is one of the application areas which can use more parallel compute power. But it works the other way around too … tools for virtual platform development and deployment can be instrumental in developing embedded software for multicore architectures as well. Especially the enhanced debug insight allows users to check for race conditions, deadlocks and stalls – i.e. the typical multicore nightmares.

So, life is still interesting here at DAC – multicore is changing the landscape here in EDA and ESL land as well! DAC will go into its final stretch tomorrow, so this is the last update from DAC.

I’ll be off to Orlando to the Freescale Technology Forum next week. If you are there please visit us, we will be showing an Freescale I.MX31 virtual platform running Windows CE and will show you how to do power analysis and early software development on it. See you there !

Ok, my calls have been heard. Here you see us on day 2 chatting away in the Synopsys booth. TLM-2.0 has been very well received and one of the topics of interest is how to further enhance the ecosystem now that the models have become fully interoperable. A lot of ESL service providers are also interested to partner further so that we can provide better joint solutions to you, our customers.

I’ll be here again on Wednesday from 2:00pm to 3:00pm (pending when I’ll actually leave the Denali Party …). Come visit for an ESL chat and how it is now all about the models (the SystemC TLM-2.0 compliante ones that is).

Monday kicked of here in Anaheim with announcements of OSCI introducing the completion of the SystemC TLM-2.0 API standard. We at Synopsys sent out a release in parallel documenting our support.

At lunch we had panel called “Real World Advantages of the OSCI TLM-2.0 Standard for Model Interoperability and IP Reuse”. The moderator was Ron Wilson and his technical style served the discussion very, very well. On the panel we had four user representatives:

• Ken Tallo of Intel, Director of Virtual Platforms Group in Intel’s SoC Enabling Group
• Prakash Rashinkar, Rambus, Director of Engineering
• Tauseef Kazi, Qualcomm, Principal Engineer/Manager
• Adam Donlin, Xilinx, Senior member of the Performance Analysis and Verification Team

To start with the best at the beginning  … the overarching theme of the panel was that TLM-2.0 is ready and worthy for widespread adoption.

The panel format worked very well. We had no PowerPoint. Instead Ron was asking in front of about 180 attendees opening questions to give each of the panelists a chance to introduce their position. Ron opened the floor with the question on what impact TLM-2.0 will have on the panelist’s organizations and what its advantage is.

Tauseef Kazi from Qualcomm welcomed the TLM-2.0 release and mentioned that they “have been waiting” for it. The standards availability will make it easier for Qualcomm to convince their teams to use interoperable system-level models. They have plans to use it right away.

Prakash Rashinkar from Rambus introduced their memory related technology and emphasized Rambus’ need performance models to go with them. In the past customers demanded models using specific APIs. SystemC TLM-1.0 was not providing enough interoperability, which they hope to achieve now for their customers and themselves with TLM-2.0.

Ken Tallo from Intel confirmed that Intel is planning to use the standard. He sees two points of immediate impact. First, TLM-2.0 will help them manage complexity. With TLM-2.0 they can provide virtual platforms and enable their software developers to start pre-silicon software development earlier. The second issue is cost, for which Ken sees going forward TLM-2.0 models representing the soft IP they already buy from vendors and develop internally.

Adam Donlin from Xilinx sees as primary use model the architecture analysis. They also see cost as an important issue as these models are difficult to develop. He also indicated that standards like TLM-2.0 are necessary as removing volatility.

Ron then continued his opening questions asking what else will be needed and whether the memory mapped approach in SystemC TLM-2.0 will be sufficient.

Adam replied that he is not so concerned because memory mapped model meets their use model. The software focused use model of TLM-2.0 for virtual platforms makes a lot of sense to him. What he would like to see more leadership in is a better definition what the specific use models are for which TLM-2.0 users. In this context he asked for a performance analysis cook book.

Ken looks at TLM-2 as a layered framework. Depending on which users he talks to they need different accuracy levels. Specifically he differentiated between System Architects and Micro Architects, the latter requiring more detail.

Prakash is encouraged that this is a very good start given that older models had lots of performance issues. Depending on the customers they need different accuracy levels and TLM-2.0 provides the appropriate infrastructure for that.

Tauseef again pointed out the focus of TLM-2.0 on software development. At Qualcomm they also need some notion of cycle accuracy in their models for architecture analysis. For some of the functionality in special protocols he expects some extensions to be done. The debug interface is currently missing and extensions to the two passed approach will be necessary.
Ron continued with his closing opening question whether TLM-2.0 is really a platform for software development or whether there will be other things developed within the infrastructure as well.

Ken Tallo pointed out that we are just scratching on the concept of ESL. In a panel two year ago he had predicted that there would be more software companies at this DAC and while there are certainly more vendors, he sees the industry converging around TLM-2.0. The complexity of the hardware is getting more and more difficult to manage, and for the pre-silicon software development there is a lot to be gained from what we have with TLM-2.0 now. Further refinement can happen within this platform.

Prakash added that their customers have been quite happy with what they are getting from SystemC TLM-2.0. Prior to using SystemC they were using proprietary C++.

Finally Tauseef described that they had different SystemC model flavors in the past. The TLM-2.0 specification points out early on that it is best suited for more abstract development. He would like to see more detailed cycle accurate requirements in the future to be able to quantify it side by side with RTL. In reply Adam chimed in that they at Xilinx had started with cycle accurate model because they were least contentious. But there is just not enough simulation horsepower to answer all the questions at this level of abstraction as they showed in benchmarks at NASCUG. The communications interfaces provided by TLM-2.0 are nice, and what he would also like to see going forward is real tool interoperability.

Then we were up for questions from the audience. The first question was about model validation. The panel and what conformance validation techniques the industry might need going forward. The panel unanimously agreed that verification of models is a key issues, and that there even some compliance testing may be required. This may be a business opportunity! When asked what the compelling event would be for vendors to “retro-fit” their models to support SystemC TLM-2.0, Adam came back with my favorite response of the day: “It’s irresistible – think about the thousands of designers who will come out of school being trained on SystemC TLM-2.0”. Go Adam! The panel widely agreed that TLM-2.0 is definitely worthy of widespread adoption and that users should not wait for next versions.

There was some open discussion about how to add more accuracy to the models in TLM-2.0. Ken came back with the comment that the “software guys are ecstatic about getting anything prior to silicon”. They do not like hardware and he sees it likely that virtual platforms are still used after hardware is available. He agreed that there are some applications for which timing accuracy is required but questioned whether they can provide it. In many cases gross cycle accuracy is enough. Adam commented that they are trying to cross calibrate with as many places as they can. The question to him is how well this will be supported in the coding style and the programming models. He definitely see s in the future a three phased protocol required.

Mark Burton from GreenSoCs, who had earlier that day effectively retired their “GreenBus” in lieu of supporting TLM-2.0, commented from the audience about the release of TLM-2.0. He stated that we are perhaps “watching the birth of ESL and perhaps are not making enough fanfare about it.” He added that the results “effectively have pleased everybody in the community” and that the download kit contains “fantastic improvements compared to the draft release”. He asked the panel on their recommendation how to adopt TLM-2.0. Should it be the hardware or the software engineer?

While Ken was very clear that the hardware engineer should write the models, Prakash mentioned that at Rambus they have designers with backgrounds in both hardware and software. Adam added in that the models should come from vendors which in turn brought up a question on customer interaction. Prakash mentioned that models can be used for early specification of behavior and customer interaction, they sometimes even allow customers to participate in early specification. For Tauseef and Ken the majority of customers are in-house users and Adam explained that for Xilinx use of models is mixed between internal and external users.

In summary this panel was a great snapshot of what users think. Yes, there will be enhancements in some areas like debug interfaces, but everybody agreed that SystemC TLM-2.0 is a giant step forward and ready for adoption.

So, I have to admit that I am a bit oldfashioned and that this blogging is a little new for me. Janick and I are sitting here in the Synopsys booth and are blgging away. Come visit us for technical chats if you like - the booth is comfy and fun, they are doing a killer coffee here and the technical discussions are great!

The first day is going into the final stretch here … Attendance seems to have been OK. I was mostly in customer meetings and a really well attended OSCI panel, about which I’ll write tonight.

If you are in Anaheim – come see us here at the Synopsys booth!

Well, we are here, finally! After Synopsys contributed key technologies in early 2007 the age of proprietary virtual platforms seems to come to an end with the announcement that the TLM-2.0 API for transaction based interoperability has been finalized. We at Synopsys immediately announced that we are fully endorsing the standard and that we will support it in our DesignWare System-Level Library and Innovator product lines.

Why is this important? Well, over the last decade the virtual platform industry with the three V’s Virtio, VaST, Virtutech combined with ARM-AXYS and CoWare have basically saturated the early adopters in this market. What was hindering the market to further proliferate is now no longer an obstacle – the interoperability of models. As indicated in this figure the introduction of TLM-2.0 is really like the standardization of Verilog and VHDL which eventually led to the demise of proprietary HDLs. With the introduction of TLM-2.0 the proprietary APIs for fast virtual platform development will eventually be replaced with SystemC TLM-2.0.

The Fujitsu quote in the Synopsys press release says it all:

“We recognize the need for system-level solutions that improve the efficiency of pre-silicon software development as well as complete system verification, and interoperable models are key. The TLM-2.0 compliant SystemC models delivered in Synopsys’ DesignWare System-Level Library are a valuable piece of an ESL design methodology enabling the rapid development of virtual platforms.”

Takashi Hasegawa
Director, ESL & Verification Department, SoC Design Engineering Division
Fujitsu Microelectronics Limited

So, technically, what are the key deliveries of TLM-2.0, for which the OSCI announcement has been endorsed in its quote sheet by almost 30 companies?

TLM-2.0 defines the interoperability standard that allows model reuse for software development and performance analysis as well as architecture analysis. The actual features supported include generic transaction payload for memory mapped busses with payload extension mechanisms allowing users to instrument their virtual platforms with timing in loosely timed (LT) and approximately timed (AT) modes. The adoption of TLM-2.0 minimizes the need for bridges or adaptors to connect models together and it supports multiple, compatible abstraction levels. As a result users get high simulation speed, debug and analysis and interoperability with the earlier versions of TLM-1.0.

Documentation, training and examples are available for download from http://www.systemc.org/home.

We will have a user panel discussion with the theme “Real World Advantages of the OSCI TLM-2.0 Standard for Model Interoperability and IP Reuse” today at 12:00 noon in Ballroom E of the Anaheim Convention Center. I will let you know what these users have to say. For the time being I am leaving you with a positive outlook on the virtual platform market by quoting Gray Smith from our Synopsys press release:

“In our 2007 ESL Market Trend Report, we predicted more rapid growth for virtual platforms once the standards issues get resolved. Standardization of TLM-2.0 removes an important hurdle for virtual prototyping to enter mainstream adoption and to more closely link embedded software and hardware development.”

Gary Smith
President of Gary Smith EDA

I am at the Design Automation Conference here in Anaheim this week. While my three-year old daughter has her first Disneyland experience (go princesses!) I am attending several sessions and panels, but will mostly interact with customers.

The Sunday here at DAC kicked off with the EDAC Executive Reception, which was distinctively different this year.  After the typical networking they had brought on a panel with the game show theme “It’s Time to Play Differentiation” moderated by Ron Wilson. Wally Rhines played a fictitious OEM trying to differentiate a design and let the vendors push their buzzers to explain how they would differentiate. Wally came up with requirements for the “MyPhone”, a smart phone consuming very low power, having an HD display, supporting any broadband source in any country and also being an open platform, i.e. independent vendors can add applications.

Representatives from Virage, TSMC, Synopsys, Magma, ARM and Analog Bits were commenting in an entertaining way on their differentiation prompted by riddles coming from Wally. Well, what we already knew in the Synopsys SLS team – that it’s all about the models – came true here as well. Given that all  this happened in Southern California, two quite eye-catching models (female and male to keep the balance) were brought in to present various envelopes, applause signs etc. I can’t really post pictures without getting in trouble with our Marcom police, but use your imagination.

Bottom line though several ESL related issues were emphasized really well – design for low power, design flexibility with multi-standard support and support of an open platform for programming! Oh, and the Industry’s Gadfly John Cooley got voted off the EDA industry in the process. He seemed to have re-appeared though later in the evening.

The evening continued with the General Chair’s Reception. Opening  speaker was NVidia’s Chris Malachowsky with a pretty cool talk about the power of heterogeneous computing, their Tesla GPU architecture and the CUDA programming model to allow efficient programming of multicore architectures.

From a system-level perspective the CUDA programming model is an interesting one to follow as we seem to arrive at several new programming models for the different application segments. CUDA is especially effective for graphics applications, but Chris also reported impressive 17x to 149x improvements in performance for other applications like physical computing and signal processing.

Next on was Mary Ann Olssn from Gary Smith EDA asking the question “whether this is the year of analog?”. All industry indicators seem to imply that it is …

Bryan Lewis from Gartner talked about the transformation of the ASIC domain, nicely summarizing major industry trends like acquisitions  (LSI: Agere, Marvell: Avago), TI’s exit from leading edge process development and Nokia’s outsourcing of ASIC design to ST. The key outcome seems to be that nobody can do it alone in the semiconductor industry anymore and that the actual system-level knowledge is shifting around with ASSP providers again doing more ASIC like designs and system companies doing less chip design.

As a result Bryan sees a fragmentation of the ASIC market between leading edge designs producing big dollars and mainstream designs using older processes (especially in Asia Pacific). He foresees further supplier consolidation at 32nm ASIC designs. In addition design reuse will increase with more ASICs being derived from ASSPs and finally vertical application focus will be crucial with software supporting it on platform based products with lots of unique IP.

Last on stage was Gary Smith from Gary Smith EDA. His presentation was titled “FUD, Reality and Vision”. First Gary addressed some of the FUD around. He attributed the alleged semiconductor recession to memory pricing problems and countered the claims that there may be only a hand-full of Fabs in the near future with the prediction there will be a handful Mega-Fabs and Mini-Fabs making a comeback. Instead of the often predicted further consolidation of the semiconductor market, Gary took the position that there will actually be an expansion, with many of the older semiconductor vendors disappearing and being replaced primarily by Asian semiconductor vendors.
Finally Gary countered the notion of the EDA industry maturing with the information that they added 62 new EDA vendors to their analysis.  Gary sees only the RTL portions maturing but not ESL, which grew 50% in 2006 and is projected to have a 47.4% five year CAGR. Exciting times for ESL!

On embedded software Gary showed an interesting analysis based on the software cost chart coming from the 2007 ITRS data . He took the graph on the right, Figure DESN1, “Impact of Design Technology on SoC Consumer Portable Implementation Cost” (from page 2 of the report on design) and re-drew it assuming the industry does not deal with parallel processing , assuming that there will be no concurrent SW compiler partitioning software across multiple cores and assuming that the industry does not deal with heterogeneous parallel processing. The resulting, modified graph had a peak in 2015 with an overall development total being at around $500M (compared to less than $100M with productivity improvements) and software development consuming the lion share of it. Well, let’s hope we all will figure it out and can avoid such an disaster …

Gary closed with a list of top ten issues for 2008. Among them were tools for multicore programming (2), a new embedded software language (3), FPGAs becoming a true system development platfom (5), intelligent test bench (6), the battle for the virtual platform market (7) and the question on how to reach 80% to 90% die re-use (10). This means that more than half of the top ten issues are predicted to be system-level issues!

In summary the evening left one with the impression that embedded software and electronic system level issues are key drivers over the next years to come. This promises to be an interesting DAC for ESL again!

Never let the future disturb you. You will meet it, if you have to,
with the same weapons of reason which today arm you against the present.
Marcus Aurelius Antoninus (121 AD – 180 AD), Meditations, 200 A.D.

So this is my attempt to define ESL. Well, while the term has been coined quite some time ago by Gary Smith, I would claim it still is in its beginning. Predicting the future is difficult, to say the least. But call me German and overly structured, but I think we can learn from the past. Today the ESL space is pretty fragmented. Generally everybody who deals with the pre-RTL aspects is counted in this category. There are several sub-categories, probably best described as a comparison what we have at the RT Level.

This graph shows how the industry moved up in abstraction levels so far, this time it indicates also how you move between them. Without exception at each abstraction level so far we had the following categories:

1. Verification at the next higher level of abstraction. Example: In 1992 I developed a HDTV Motion Estimator Chipset for a telecom provider. The design was at the gate-level. But to verify that the six chips interacted correctly we used RTL for verification as it was much faster.

2. Equivalence checking within and between abstraction levels. Example: Equivalence checking from gate to gate was driven by the need to verify that the optimizations did not screw up the intended functionality. The same was true at the RT Level. The next step was to verify between RTL and Gate that the functionality had been maintained given all the optimizations predicting implementation aspects.

3. Synthesis from one level to the next. Example: Once the appropriate synthesis subset of a standard language like Verilog had been defined logic synthesis from one level to the next started taking off.

There are similarities when we look at the pre-RT Level in which the set of ESL tools play today.

1. Verification at the pre-RT Level. This is what Gary Smith I think calls the intelligent test bench. This has been the first part to take off at the RT-level and with moving verification to the transaction level it has been the first part taking off in ESL too. The usage of SystemVerilog transactions for verification documents that. The interesting change this time around is that things do not only get more complex but we have a new component in the system – embedded software is required to model a system completely as verification reference. And that’s where we are facing a bit of a dilemma, given that software designers and hardware designers are quite different. But the next and new category, virtual platforms, offers a valid solution.

2. Virtual Platforms at the pre-RT Level: Including Synopsys there are several players in this field. A virtual platform virtualizes the hardware to allow efficient pre-silicon software development and to compress project schedules by allowing the development of post-silicon tests to be started early. There are other use models for virtual platforms, mostly around performance analysis and optimization. The requirements with respect to accuracy and speed depend a lot on the targeted application domain. Real-time software for example seems to require generally more accuracy in the modeling of the underlying hardware.

3. Equivalence Checking: The first companies in this domain (SystemC to SystemC and SystemC to RTL) are out, although they are in early stage.

4. Synthesis from SystemC to RTL. Several companies like Mentor and Forte provide offerings in this space. Now that the industry has a standard language (SystemC) and as we are getting close to a behavioral synthesis subset definition with SystemC, this area probably has room for growth.

Virtual platforms are one of the main drivers for the ESL area today. As an example this figure illustrates in the bottom a generic block diagram with protocol blocks, busses and processors at the signal level. Transactors used in verification IP are utilized to drive signals based on transaction input. The top portion of the diagram shows the corresponding block diagram as virtual platform at the transaction-. At that level of abstraction, connections to real world I/O of USB, Ethernet, SATA and PCI, as well as skins and virtual representation of the actual device can be used to interact with the virtual platform.

Independent of language questions the transaction-level is the undisputed next abstraction level above RTL.

With the standardization of the TLM-2.0 API, SystemC now offers a very suitable infrastructure for fast execution of virtual platforms. With processor models by itself reaching speed levels above 100MIPS, full platforms of several processors and peripherals can be integrated in SystemC using TLM-2.0 and still run between 20 and 50 MIPS at the platform level. Furthermore, SystemC is already well integrated with the rest of the design and verification flows – all bigger simulation vendors offer SystemC support in their mixed-language simulation engines. This makes it the perfect choice for virtual platforms for pre-silicon embedded software development and – once available – linkages to verification.

I am looking forward to your comments! But please remember:

Prediction is very difficult, especially about the future.
Niels Bohr (1885 – 1962)