Archive for the 'HSIC' Category

Here’s the longer, more detailed version of our USB 3.0 SSIC demonstration.   It’s 7 minutes.  It’s going to be the best 7 minutes of your day.

SuperSpeed Interchip Proof of Concept–Long Version

If you want to watch the shorter version (or more of a description) go back to last week’s blog here for a written description of the SuperSpeed USB 3.0 Interchip (SSIC) demo.

I meant to post it Thursday last week, but apparently I lied.

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Last week I wrote “…someone pointed out to me that no one is going to ever watch these videos twice.”

I received this comment in response, “Eric you are right, I’m never going to watch theses videos twice”

Thanks.

Thanks very, very much.

Synopsys worked with the USB-IF SSIC Working Group to develop a SSIC Proof of Concept demonstration. 

The USB-IF has been working on SSIC for some time.

This Proof of Concept in FPGA is to test the SSIC specification version 0.90 to see if it actually works in hardware.

It worked (mostly).

We learned, as expected, the SSIC Spec needs changes.

We learned what works and fixes need to be made to the specification.

We used our own HAPS FPGA platforms and standard PCs.  The HAPS51-2s are connected to the PCs with PCIe.  The FPGA boards are shown below.

On top (left side of table) we have a modified USB 3.0 Host for SSIC.

On bottom (right side of table) we have a modified USB 3.0 Device for SSIC.

There is no USB 3.0 PHY in this set up.  Read to end for more on the PHY used.

Take note:  FPGA-Based Prototyping is a good idea as part of specification development too.

As with our standard USB 3.0 Host and Device, we could close timing in the FPGAs at 125MHz even when the FPGA design is over 80% utilized.

We’ve edited 2 versions the SSIC Proof of Concept video for your viewing pleasure. 

A short version and a long version.

The short version focuses on the hardware setup and the demonstration.  It’s posted below.

SSIC Proof of Concept – Short Version

This is Shailesh and I just before we started the demo.

What is the point?

The SSIC USB-IF WG has both proven the SSIC concept works, and improved it using FPGA-based prototyping.  The USB 3.0 can be used with the SSIC modifications to use USB 3.0 on PCB for chip-to-chip communication with less power than USB 3.0 outside the box.  It preserves software so you continue to use existing USB 3.0 drivers and stacks.

What is SSIC?

See the previous entry here for a brief description.

It will be used to connect Applications Processor chips to other USB 3.0 peripherals inside the box, on PCB.  It is a chip-to-chip protocol. 

For example, it could be used to connect a Mobile Apps Processer to a WiFi baseband chip.  The Apps processor could use the same, unmodified USB drivers it uses for an external, USB plug in WiFi modem.   It uses USB 3.0 to communicate, but it can less power because it drives signals over a few centimeters of PCB, not 3 meters of USB 3.0 Cable.  SSIC uses a different M-PHY for SSIC.   It uses less power.  We don’t use an M-PHY in the SSIC Proof of Concept.

 

Caveat and Disclaimer

This is not a product and this is not a product announcement.  This is a working demonstration of the technology.

Read to the End

The long version is 7 minutes and has a lot of detail and is only for the most brave USB viewers.   It has a more detail detail on how the two boards are connected.  So I lied.  There is no detail how the two platforms are connected when the USB 3.0 PHY is not used. You have to wait until Thursday and watch that video.

See you Thursday.

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I wanted to post the short video first and post the long video later, but someone pointed out to me that no one is going to ever watch these videos twice.

So I separated them anyways because you were going to come back on Thursday anyway.

Tomorrow, I should be posting something of interest to you on SuperSpeed Interchip (SSIC).

If all goes well.

SuperSpeed Interchip (SSIC) brings USB 3.0 from outside the PC to on the PCB to use USB 3.0 between chips.  It allows you to reuse your USB 3.0 software drivers and take advantage of USB 3.0 gigabit speeds to communicate between chips on the circuit board. 

More tomorrow.  Most likely.

Yes, this is a terrible blog entry.

You try to write something 12,213 people want to read at least once a week.

Something that isn’t a Facebook update status like, “Love the Fried Dumplings in Beijing”

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I like Fried Dumplings, Steamed Dumpling are good also.

I’ve worked on little things like business reviews and integrated product plans the last several weeks.

In the meantime, I’m going to start catagorizing these entries as one of 3 things

1)      Marketing

2)      Technical Light

3)      Technical Heavy

4)      Synopsys Marketing

5)      Tech Life

6)      Rants

Okay, one of 6 things

This way you can decide if you really want to read the entry or not.

Several weeks ago we announced availability of our HSIC and LPM offerings in the PHY, controller, and verification IP fields.

Make no mistake, we actually have a complete, complete offering.

(I hate the word “solution”, it has no meaning since about 1999)

(Maybe before that, but my memory starts in 1999)

This means if you are building a chip with USB that needs these features, you can get 3 elements that you need.

The LPM feature on the PHY allows you to turn the PHY and controller faster on and off faster.  This means you can actually put your devices into a suspend mode more often because you can reliably turn the USB back on quickly when you need power.

This means optimizing the PHY and the controller timing to guarantee the faster on-off times.

The HSIC feature added a high-speed only path to connect to the Synopsys HSIC PHY.  The PHY consists of only the digital portion of the PHY and can be used for chip-to-chip communication on a PCB.  You don’t need 3.3V signaling for HSIC.  So you save power.  You can use standard USB drivers as well.  So if there is a USB device or peripheral chip (and there are lots) you can add an HSIC PHY to it, and make it an on PCB chip.  Similarly you can add a Host to an Apps chip to allow expandability using HSIC Host ports.

For example, in an STB, you could put a standard USB 2.0 EHCI Host on the PCB, run Linux on the board, and run multiple ports from the Host Controller.  Some of the ports could go outside the box, like on a Tivo box for a USB WiFi dongle.  Some of the ports could be used internal to the box on the PCB.  In this case an HSIC PHY would also be integrated into the chip.  HSIC lines would be drawn from the host port on the chip to another peripheral chip, say a SD card reader for reading SD cards plugged into the front of the set top box.   In this way, the HSIC allows use of standard USB Mass Storage, but uses less power and less area because the PHY is smaller (no analog) and the voltages required for HSIC are lower.

Verification IP from Synopsys – As you might guess, we heavily verify all our digital controllers with our Verification IP or VIP.  The VIP has both the LPM and HSIC features added in by this summer.  This is the same VIP that we run through our extensive constrained random verification suite for the controller.  The benefit is that the VIP gets a thorough verification both with the controller and in a stand-alone mode.  It’s actually verified twice completely.

We provide the same, well-verified verification IP for our customers to use.

(I also hate the word “very”.  My feeling is that using this word has even less meaning that the term “solution”)

HSIC High Speed Inter Chip LPM Link Power Management