Archive for the '2. Skirmishes, Battles and All-Out Wars' Category

There is more and more talk about the need for standards and interoperability in 3D. We mean 3D ICs – stacking chips in a single package – not to be confused with 3D entertainment which also is looking at creating standards such as those for 3D glasses.

And there is more and more action being taken. Several standards organizations have formed groups to study and/or develop standards for 3D ICs. These include: JEDEC, SEMI, SEMATECH, SIA, SRC, IEEE-SA, IEEE-ISTO, GSA, and Si2. It’s not surprising for a new technology to receive a lot of attention from the standards arena. There are technological and business challenges to overcome that can be helped by the introduction of appropriate standards. As the working groups sort out what’s needed, who will do what, where competition and cooperation should exist, and which standards will be adopted over others, there could be (OK, there likely will be) the usual turbulence that accompanies all standardization journeys.

The topic of 3D IC standards will be one of the discussions that will happen at the 18th Electronic Design Process Symposium (EDPS). The April 7-8, 2011 symposium will be sponsored by three of IEEE’s subgroups: Computer Society of Silicon Valley, Council on Electronic Design Automation, and Design Automation Technical Committee.

I’ve attended EDPS in the past and found it to be especially interesting because of its small, intimate nature. Presenters and attendees are there because they are passionate about their topics. If you’re interested in 3D ICs, you might find value in spending a day in Monterey CA discussing your views and asking questions of other participants.

Other topics at EDPS will include:

• Parallel EDA
• High-Level Design – including Requirements-Driven Design Flows
• Cloud computing – including Software as a Service
• Low-Power Design – with Solution Mapping to 2009 ITRS Roadmap

To see the program schedule and more information: www.eda.org/edps

To register directly: http://edps2011.eventbrite.com

The topic of 3D IC standards is likely to step to the forefront of the standards game in the coming year or two. Fasten your seatbelt.

There’s been a shift in what’s needed in modeling standards for IC design. The focus has moved from timing to power consumption. Timing modeling, which dominated much of the effort from the early to mid 00’s, has sorted itself out. The Liberty format (.lib) has been successfully extended for demanding nanometer timing accuracy by customers and EDA suppliers via collaboration in the Liberty Technical Advisory Board (LTAB). Other groups such as OMC that had sprung up to tackle timing modeling, among other things, have completed their missions and provided direction to the LTAB so that Liberty (.lib) consolidates all the market needs.

Power management of ICs is now the growing challenge, as power modeling and optimization has replaced timing as a critical need for standard modeling during the past couple of years.

Power consumption has to be modeled at both the gate level and the system level. A lot of good work has gone into power modeling at the gate level in Liberty, and this work is ongoing. Several years ago, the LTAB ramped up its efforts in the area of power modeling, in conjunction with the rise of UPF and CPF power formats. Both the IEEE 1801 Low Power Working Group and the Si2 Low Power Coalition (LPC) have been guiding critical extensions to Liberty with respect to gate-level and macro-level power and implementation modeling. The LTAB accepts input from all sources – one doesn’t have to be a member to contribute.

This cooperation with IEEE 1801 and LPC is a good example of the First Commandment for Effective Standards: Cooperate on Standards, Compete on Products. The concept is that it’s most effective and efficient for companies to cooperate on creating standards. The corollary is that, just as for companies, it’s better for standards organizations to cooperate. IEEE 1801 and LPC contributing to the LTAB is the model of cooperation among standards organizations that we can always use more of.

What’s coming next for power modeling? The challenges are moving into the system-level space – ESL if you like. As in moving from transistor-level to gate-level modeling, moving from gate-level to system-level means new and/or enhanced standards are needed. Taking power modeling up a level of abstraction, to the transaction-level, will require a lot of system-level expertise that needs to come, not from the gate-level world, but from another space – the system-level space. Power modeling efforts from the system-level experts will be essential to produce effective standards. The system-level guys will certainly need to play a substantial role.

Just where are the system-level guys? In OSCI, of course. The Open SystemC Initiative has been the center point for system level modeling since 1999. It only makes sense for system-level power modeling standards to come from OSCI. In the same spirit as the LPC cooperates with the LTAB for gate-level power modeling, it will be great to have IEEE 1801 and LPC contribute valuable ideas to OSCI as they generate new system level modeling needs.

I have a new friend in the standards game. His name is Keith Boone, and he works on standards in the medical industry for GE’s Healthcare division. Keith’s recent blog post, “Tactics for standards setting: lead, follow, or get out of the way”, gives insights that pertain to challenges anyone in any industry faces while creating standards.

The 5 tactics Keith writes about are: ignore, monitor, contribute, lead, and kill. He adds an interesting dimension to playing the standards game – that of budgeting. For each of the 5 tactics he describes, he provides the relative costs (in time and travel). Leading costs more than monitoring, for instance.

As in the medical industry, these tactics are also used in the electronic design automation industry. I’d like to highlight a couple of points in Keith’s post and add some insights from EDA.

Ignoring a standards effort in EDA is appropriate when the proposed standard brings no value to our products and services. It’s my Seventh Commandment for Effective Standards – Think Relevance. The standard may not go away completely (especially if there are a few players who think the standard is cool), but most parties will not incur unnecessary, wasted costs.

Monitoring happens a lot in EDA standards. It seems that it’s usually the big companies and a handful (at most) of smaller ones are the major contributors to our standards. The rest simply sit back and watch for the right time to capitalize on the standard by supporting it in their products. Case in point: look at all the companies that support SystemVerilog and compare it to the names of the participants in its development.

When it comes to EDA, contributions are the key to success of our standards. Starting from scratch is rarely a good way to begin a standards effort. When we say “contributions”, we mean – as Keith states – commenting on email reflectors, participation in discussions and conference calls, attending meetings, providing feedback during voting / balloting, and providing text. We take it one step further and contribute technology as well.

Leadership is an absolute requirement for a successful EDA standard. No matter what other tactics may be in play, it’s leadership that will ensure a viable standard is the result. I’m not sure that 80% of the contributions are uncontested in EDA (that would be nice). We’ve certainly been through some big battles. However, I could probably find some cases that match the 80% figure, and I’d bet it was leadership that made them that way.

There’s no doubt that “kill” is a tactic that is repeated in EDA. The element that Keith describes which seems to be missing too often, though, is transparency. If we were to follow his advice, it’s possible that there would be a lot less positioning and posturing – especially in the media. (I’d like to point out that IEEE-SA has similar balloting rules as ANSI and ISO that help enable the delaying tactic.)

I thoroughly enjoy reading Keith’s blog (and following him on Twitter) and seeing how similar industries are when it comes to producing standards.

Toyota has been in the news a lot lately. Something you might not have heard about is the standards battle they’re involved in. It’s an interesting situation and the stakes are high. The automobile industry is moving into a new era of engine technologies. And there’s an “engine format war” being waged. Which will win – the petroleum/electric hybrid or pure electric?

Toyota firmly believed in the hybrid engine and invested huge sums in its development.To date, it has produced more than 25 million hybrid vehicles. Yet other companies, such as Mitsubishi, and Nissan, thought otherwise and have since developed affordable all-electric vehicles.

In May of this year, Toyota announced an alliance with a small startup company, Tesla, to jointly develop all-electric cars. And Toyota is making a sizable ($50M) investment in Tesla. Tesla, based in Palo Alto CA, has delivered more than 1,000 sporty roadster vehicles which currently retail for about $110K. (That’s expensive for most auto consumers.)

Last year, the state of Colorado gave residents a $42,000.00 tax credit to those who bought a Tesla. It was part of an incentive program to get people to buy low-emission cars. (I didn’t buy a Tesla, even at the “bargain” price of $68,000.00.)

In Colorado, where I live, the name Tesla has special meaning. Nikola Tesla moved to Colorado Springs in 1899 to do research and experiments with high-frequency high-voltage (millions of volts!) electricity. Tesla is well-known as the brilliant scientist who invented the AC motor. Without this invention, the world’s electrical power might have been DC instead of AC. Talk about a standards war – the DC-AC one was a doozy, with animal electrocutions, life-threatening challenges, and eccentric personalities being the order of the day.

In the present standards struggle, does Toyota’s interest in Tesla mean they have conceded the hybrid’s days are doomed? Is Toyota making a bold move into the all-electric vehicle to prevent losing the engine format war? Or will the automobile industry continue to support two standards? We’ll know in a few years.

In writing my book, “The Ten Commandments for Effective Standards”, I explored standardization challenges outside my regular field of electronic design automation. I was not at all surprised to find an abundance of stories about standards struggles in all kinds of industries. (Several of these stories are cited in the book.)

EDA is not unique in facing challenges in standardization. The boundary conditions of our business are not to blame. Blu-Ray and HD DVD, anyone? Our customers are not to blame, either. Standards – when they’re effective and even when they’re not – can have a profound impact on any industry and its consumers. My tenth commandment says, “Know that Standards Have Technical and Business Aspects”. It’s no wonder, then, that companies (whose purpose is to remain and be successful in business) don’t always jump at the chance to collaborate with their competitors. This is a global situation.

And yet, in the EDA industry, we have been able to cooperate on standards while competing on tools. Take SystemVerilog, for example. It’s arguably the most widely adopted standard in EDA history, especially since it was built as an extension of Verilog. At the beginning of its standardization, EDA companies questioned whether it would be an effective standard. Once it was clear that customers did need and want it, EDA companies – including the “big 3” leaders – pooled their efforts, produced IEEE Std. 1800, and embraced SystemVerilog. The number of products and solutions that support this standard is witness to the positive outcome of cooperation, and not just from the two largest EDA vendors.

Cooperating on standards efforts is challenging not just for companies, but for standards organizations as well. For example, the CPF / UPF “war” could have been settled if Si2 and Accellera had found a way to cooperate. As with commercial companies, standards bodies have business aspects as well.

I continue to hope for more cooperation among companies and standards bodies. Perhaps people will try some of the suggestions on how to do this from ‘The Ten Commandments’. Time will tell.

P.S. My book will be available on Amazon and other outlets at the end of May.

Congratulations to Accellera’s Verification IP Technical Subcommittee (VIP-TSC) for reaching yet another milestone on its journey to achieve harmony among verification standards. The near-unanimous desire and commitment to create a Universal Verification Methodology is an indication of the still growing need for collaboration among verification engineers, verification IP vendors, service providers, and tool suppliers – and their faith in Accellera to do so as an open standards organization.

In my October 1, 2009 blog post, A milestone completed towards verification standards, I wrote:

Now it’s time for the group to start working on their “long term” standard. Their efforts will produce a common base class library that can be used in simulators from multiple design automation tool vendors. The common base class library will foster a broad (universal) verification methodology to benefit verification engineers and developers of verification IP.

Again I’m optimistic that the VIP-TSC will provide the industry with an effective verification standard. Hmm. Maybe they will call it the Universal Verification Methodology (UVM).

According to the status report from the VIP-TSC, the next phase of their work is indeed called the Universal Verification Methodology (UVM)!! I’m pretty sure the working group didn’t refer to my post when deciding on a name for the standard, but it’s fun to see a prediction come true nevertheless.

And now it’s time for the group to start working on their “long term” standard. Their efforts will produce a common base class library that can be used in simulators from multiple electronic design automation tool vendors. The common base class library will foster a broad (universal) verification methodology to benefit verification engineers and developers of verification IP.

The VIP-TSC working group that will now tackle UVM appears to be focused on a critical aspect of standardization – delivering not only a specification but also a usable reference implementation. In the short-term phase of their work, they created an interoperability guide, and now they will work on providing a single UVM library that will reflect the best of VMM and OVM. This is what I like about an industry collaboration that’s focused as much on deployment of a standard as it is on the creation of it.

I’m glad to see this open, inclusive, and timely standard coming to life with support from a wide-ranging verification community. Synopsys strongly endorses this UVM effort under Accellera. I encourage the committee to ensure that UVM not only meets immediate requirements but also builds the foundation of an industry-wide verification methodology for years to come.

Overall, big kudos to the working group  for their focus on the long term goals, their dedication, and their hard work. It’s a great way to start 2010!

I know it sounds funny, but I’d been anxiously awaiting a press release. A new standard had been ratified by Accellera, the premier standards-setting organization in my industry of chip design automation. So as not to steal their show, I had to wait until their press release came out to share the good news.

Accellera’s working group, the Verification IP Technical Subcommittee (VIP-TSC), has completed the first of 2 milestones it set out to accomplish. The working group began about a year and a half ago, and I was optimistic that they would do a good job. They decided to divide the task of producing a verification standard into 2 parts, a “short term” and a “long term”.

Their “short term” standard is now complete and is called “Best Practices Interoperability Guide”. This document provides information about using SystemVerilog verification components in an interoperable testbench environment, and it includes a reference library. It supports both the Verification Methodology Manual (VMM) and the Open Verification Methodology (OVM) which should make everyone happy in the standards game.

Now it’s time for the group to start working on their “long term” standard. Their efforts will produce a common base class library that can be used in simulators from multiple design automation tool vendors. The common base class library will foster a broad (universal) verification methodology to benefit verification engineers and developers of verification IP.

Again I’m optimistic that the VIP-TSC will provide the industry with an effective verification standard. Hmm. Maybe they will call it the Universal Verification Methodology (UVM).

The bagpipes have played at the 46th Design Automation Conference. Customers and vendors have gone home. The Moscone Center is being readied for the San Francisco International Summer Gift Fair and the Gourmet Housewares Show which start in 2 days. So it’s time for me to get back to the standards game.

I haven’t written anything about VMM since last October, but that doesn’t mean nothing has been happening with this standard verification methodology. VMM stands for “Verification Methodology Manual“, but it’s much more than a book. VMM comes with a standard library, applications, macros, utilities, and other supporting technologies – available to everyone at no cost. The latest advancements in beta now include TLM 2.0 support, block-to-top reuse, hierarchical phasing, and a lot more.  The details are available at VMM Central. In addition, the VMM for Low Power was published early this year to help chip designers prevent or overcome challenges unique to low-power IC verification.

VMM is alive and well. With 500+ projects actively deploying VMM, 50+ user papers, and tens of millions of lines of user code, it is indeed thriving. Chip design companies are continuing to adopt and leverage VMM in their verification strategies. EDA tool vendors, IP providers, training companies, and service providers are continuing to join the VMM Catalyst program (more than 60 to date). And the VMM for Low Power is receiving rave reviews.

Peggy Aycinena of EDA Confidential wrote one such review. I particularly like her summary of Chapter 8: Rules & Guidelines – sixteen simple (well, not really) rules that are detailed in the methodology for highly effective verification of low-power chips.

There’s also good progress happening in the Verification IP standard committee of Accellera. The committee’s chair, Tom Alsop, published a good article in the current issue of Chip Design Magazine describing their accomplishments to date. My favorite part is the promise that once their recommended practice document is submitted to the Accellera board for approval this summer, the committee will begin work on their long term commitment to create a common base class library.

Since the publication of the original VMM in 2005, its adoption as an industry standard has shown how valuable it is to modern chip designers.

You could say I’m nuts about 1801. I’ve written about this standard for low power design many times, such as its open environment within IEEE and Accellera, the fact that users and vendors alike developed it, and how real customers have been using it as a successful, working standard. From the day that two leading customers of EDA began a rally around “open, quick, inclusive”, to the creation of the Unified Power Format (UPF) in Accellera, to its finalization as an IEEE standard, I’ve felt it took the right direction in EDA interoperability.

In a nutshell, here’s why:

• It allows flexibility in creating power strategies without forcing customers into a pre-defined flow.
• It permits choice by users. For those who want a single file to contain their IC’s power intent, 1801 works. For those who want power intent constructs in their RTL, 1801 works.
• It augments multiple existing standards such as Verilog, SDC design constraints, and Liberty. It didn’t make sense to reinvent the wheel and make IC engineers retool. Interoperability is served well when current standards are leveraged.
• It offers support for legacy designs. Low power chip design didn’t start after low power standards were born. (Quite the opposite.) Being able to continue using existing code and methodologies can help designers reduce errors and increase productivity.
• It enables different EDA vendors to develop unique solutions, following the 1st Commandment for Effective Standards: cooperate on standards, compete on tools.

In the near future, the IEEE process for ensuring healthy standards will bring about the next 1801 project. When this happens, I’ll post information about how everyone can participate in the P1801 working group.

Today, the IEEE-SA Standards Board approved the standard known as 1801: Standard for Design and Verification of Low Power Integrated Circuits. Everyone in the field of low-power chip design has known it as UPF, the Unified Power Format. Approval by the IEEE-SA is a significant milestone in the life of a standard, and everyone who dedicated time, brainpower, and expertise to 1801 deserves a hearty congratulations and a long weekend.

The 1801 standard describes the design intent for implementing, analyzing, and verifying today’s advanced, low-power chips. With the growing awareness of energy consumption as it impacts our environment, 1801 joins a family of IEEE standards that can be called “green”. Chips that consume less power are at the beginning of a food chain of less-hungry electronic products.

From supporting the formation of and participating in the Accellera technical subcommittee for UPF, to organizing workshops, to writing articles, to working with my competitors and customers, and finally as a member of the IEEE-SA Standards Board, I’ve been involved in 1801 from start to finish. Along with many of my respected colleagues, I experienced the excitement and struggles that occurred throughout the process of producing 1801. While my role was largely in the “business” aspects of developing this standard, I relished the opportunity to stay current with low-power chip design techniques. I even found myself enthusiastically giving a technical demo to a group of engineers at DAC. Wow, did that take me back in time!

Development of the Unified Power Format began in Accellera before I started this blog. I wrote several posts about it after it was transferred from Accellera, where it was first created, to the IEEE-SA under sponsorship by the IEEE DASC (Design Automation Standards Committee):

Join the P1801 working group

Is there any hope for a single standard?

UPF at the Interoperability Forum

UPF at EDSFair

UPF is a real standard with real adoption

Join the P1801 ballot group

Less visible than the U.S. Presidential ballot, but still important

What’s in store for P1801?

 You can google “Unified Power Format” for an extensive list of 1801-related materials.

The 1801 standards game was most impressive in how quickly 3 of the 4 leading EDA companies rose to occasion to work together, including their customers and all interested EDA companies, when the industry demanded an open standard for low-power IC design and verification.