Archive for the '1. Life in the Standards Lane' Category

I don’t often write about standards from the perspective of semiconductor IP. I leave that to my esteemed colleagues like Eric Huang (To USB or Not to USB) and Navraj Nandra (The Eyes Have It). I do, however, think about the importance of standards for IP fairly often. Here are some of those thoughts.

There are at least six ways that standards benefit IP. If you can think of more, bring it on!

IP is created using standards. Implementation and verification of an IP block requires standard languages and formats such as SystemVerilog (IEEE Std. 1800) and UPF (IEEE Std. 1801). Testbenches that accompany IP are written in a standard language like SystemC (IEEE Std. 1666).

Quality standards can help IP consumers determine if the IP they purchase meets the level of quality they require. The IP quality standard with the fancy name, “1734-2011 – IEEE Standard for Quality of Electronic and Software Intellectual Property Used in System and System on Chip (SoC) Designs”, is once such standard.

A standard can be implemented (and often is) as an IP block. USB, SATA, HDMI and many other interfaces are widely-used standards. They become real product features when their IP implementations are included in the products’ electronics.

The IP’s IP can be protected with standards. (OK, that was a little silly.) IP is encrypted by each IP vendor to protect it from being reverse-engineered or copied. Different vendors use different encryption, which can prevent IP from different vendors from talking to each other. A working group in the IEEE Standards Association is creating a standard with another fancy name, “P1735 – Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP)”. This standard will be able to help interoperability by providing a “generic set of embeddable markup syntax suitable for IP protection and rights management of arbitrary text files”. (That’s the description from the working group’s project plan.)

Speaking of interoperability, maybe one of the most important ways that standards help IP. An SoC design can have many IP blocks that need to communicate with each other and with custom portions of the design. I recently saw a list of standard design languages that are being used for SoCs. I shouldn’t have been surprised, but I was. The list included: C, C++, Verilog, VHDL, SystemVerilog, SystemC, e, OpenVera, and PSL. That’s a lot of standards. With mixed-language IP blocks in a single design, an obvious problem arises. The solution is a new standard based on an old one. Enter IP-XACT, “1685-2009 – IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows”. (Fancy.) It allows IP written in different languages to interoperate because it uses XML. What’s cool about XML is that it’s an internet standard, created and maintained by the World Wide Web Coalition (W3C). And it’s just plain text. IP-XACT is an elegantly simple standard to solve a big problem.

Ultimately, standards help reduce the cost of developing IP and speed its time to market. That’s definitely the most important way standards bring value to IP.

We are celebrating our 25th anniversary at Synopsys. You’ll see “25 years of enabling innovation” throughout this year. As part of recognizing our anniversary, we’re holding a trivia contest which will continue through December 2012. No doubt there will be a standards question or two.

We’ll post a question – two each month – and the first person to post the correct answer will win a $40 Amazon gift card.

You can play two ways, on our Facebook page and through Twitter.

On our Facebook page:

• If you’re not already, become a fan (click “Like” on www.facebook.com/synopsys)
• Watch your Facebook feed for our trivia questions to be posted
• Post your answer in the comment area under the trivia question

Through Twitter:

• If you’re not already, follow us on Twitter (click “Follow” on www.twitter.com/synopsys)
• Watch your Twitter timeline for trivia questions posted by @synopsys
• Tweet your answer to @synopsys

The winner of each question will be announced right away via Facebook and Twitter.

Read the full contest rules here.

The contest is underway. The first question was, “What was Synopsys’ original name when the company was founded?” The answer is, “Optimal Solutions”. (Did you know that?)

For more trivia about Synopsys and our history, visit our timeline.

Play and enjoy the game! (Almost forgot, no Synopsys employees, please.)

By now, you’ve probably seen the announcement of Accellera and Open System C Initiative (OSCI) merging to form a new, unified organization called Accellera Systems Initiative. This marks the next chapter in the history book of EDA standards organizations.

A decade ago, I was part of the core team that brought VHDL International (VI) and Open Verilog International (OVI) to form Accellera. VI and OVI were successful in their own right in the promotion and adoption of their respective HDLs (VHDL and Verilog). One could say that the formation of Accellera was due to the industry’s desire that HDLs had to grow further to help address verification, test, and power issues. Part of the truth, though, is that we were duplicating efforts and paying too much for two organizations. I’ll never forget going to a VI board meeting one day and an OVI board meeting the day after. Many of the same people were in both meetings, but some of them switched their viewpoints. I called them out for arguing with themselves.

Accellera’s desire to provide much-needed standards was realized with SystemVerilog, Open Verification Library (OVL), Open Compression Interface (OCI), Unified Power Format (UPF) and Universal Verification Methodology (UVM). Accellera then merged with The SPIRIT Consortium to expand the scope of language-based standards activity to include IP standards. Today, IP-XACT efforts under Accellera are helping integrate use of IP and its meta-data into various standards such as UVM. This is a classic example of collaboration among adjacent standards that benefits the user community with improved productivity and provides business opportunities for tool and IP vendors.

Here is some trivia about the merger that you won’t find in the announcement:

- Most of the Board makeup is the same as before (7 of 9 OSCI board members were also Accellera board members). That should bring continuity and easier integration of things like Policies and Procedures.

- There is an increase in the number of associate members. This brings the opportunity for broader collaboration and participation in future standards work.

- Logistics and infrastructure will continue to be provided by the highly capable and experienced people who’ve worked for both organizations for decades.

- Kavi continues to provide the online platform.

- Members will save money on dues and get more benefits. There, I said it.

- There is a good balance between users and vendors. Accellera Systems Initiative is not dominated by EDA companies.

- Accellera Systems Initiative will not be called ASI. That would be confusing.

- The idea of merging the two organizations came up four years ago.

As the Accellera and OSCI communities come together under a single umbrella, I believe the new organization will remain focused on the fundamental premise of EDA standards – interoperability between tools to help build robust design and verification flows. Portability of a design across multiple tools may be desirable (e.g., switching from one functional simulator to another), but it’s often not practical. It’s the ability to take the design through successive stages of refinement and validation that makes the standards most valuable.

I would like to see Accellera Systems Initiative bring the industry even more collaboration and the platform for improved interoperability across system and chip design tools in coming years. And I’d like to invite you to participate.

A final aspect on why Synopsys participates heavily in technical industry standards is one that is often missed (or dismissed): Standards enable innovation. Many people confuse standardization with stifling innovation because standards provide precise specifications. They mistakenly believe that once a standard is defined (and most importantly, accepted) in the industry, all other alternatives are doomed and no further innovation is possible. This cannot be farther from the truth. In fact, having a standard – particularly an open standard – allows the entire industry to come to an agreement about common abstractions, representations, and/or terminologies so that the communication of certain problems and solutions becomes easier and less susceptible to misinterpretation. Suppliers such as Synopsys then have a foundation upon which to build products that embody the most modern, collective thinking of the industry.

Electronic design standards such as Hardware Description Languages (HDLs) have fueled innovation for decades in the semiconductor industry. These language standards raised the level of design abstraction to help enhance productivity – that was the benefit in the early days when the industry was migrating away from schematic-based design. Further, the HDLs – initially Verilog and VHDL – allowed designers to think in terms of functions rather than structures, thereby enabling design sizes to move from thousands of gates to millions of gates. The innovations that followed came in many forms – from design and analysis tools to new methodologies and global teams working around the clock on large projects. None of this would have been possible without a common, precise language to describe electronic circuits.

More recently, the SystemVerilog HDL has allowed us to think in terms of object-oriented verification environments for the ever-increasingly complex system-on-chip (SoC) designs. The success of a “reuse paradigm”, both for design and verification building blocks and the SoCs that are designed with them, is due in large part to the standardization of HDLs, HDL-based methodologies, and other technical standards.

From a different perspective, standards enable innovations to be developed on top of maturing technologies rather than reinventing the wheel. This increases the rate of innovation – a far cry from stagnation.

In addition to HDLs, Synopsys and our customers are also beneficiaries of technical standards such as the well-known USB, Wi-Fi, and PCI. and other communication protocols/interfaces. As a leader in the IP building block business, we are able to provide standards-based design and verification IP to help our customers accelerate their product schedules. Availability of standards-based, verified components allows the precious skilled engineering resources to be focused on building innovative and differentiated products instead of reinventing the wheel of implementing standard interfaces. Our participation in the groups that create and maintain these standards means we supply IPs that are compliant with the approved specifications, and we help enable interoperability between devices adhering to the corresponding standard.

From our very beginning, Synopsys’ business has benefited from using HDL standards as input to our tools, be it synthesis or simulation. Working with our customers and the entire semiconductor ecosystem, we have developed standards-based tools and methodologies to help ensure that each design moves from concept to silicon and then into a system (an end product) in the most efficient manner. We continue to invest in standardization efforts, lead with new and innovative technologies, and collaborate with customers, partners, and competitors alike to build strong platforms that enable the advancement of innovation.

Active participation in industry standardization activities requires a long-term vision and commitment, and the benefits are tangible. We have this, and that’s why we do it.

In addition to growing the market (part 1 of this series) and establishing and maintaining technology leadership (part 2), standards promote the discovery of complete solutions in collaboration with key industry players. These collaborative solutions benefit customers, of course, by providing the best overall result which is developed as broadly as possible. Perhaps less obvious is that collaborative solutions also benefit suppliers like Synopsys. Drawing not only upon technology contributions from customers and competitors alike, but also from their expertise, allows us to create products that address a bigger set of challenges being faced by today’s advanced system-on-chip designers.

Whether our technology alone is being donated to be considered as part of a standard or it is one of several contributions, the goal is always to look for ways a new standard will help solve a wide range of problems. As a solutions provider, we certainly have insight into some of the use models that will benefit from the new standard. Often times, however, other participants in the standards development process bring additional requirements for the new standard to support use models that were previously not considered.

For example, Synopsys made the Liberty format for technology library modeling – originally known as .lib – an open standard more than a decade ago. Following that, some of the very first updates to Liberty came from recommendations by Cadence Design Systems. As process technology continued to move ahead from 180 nanometer to 90 nanometer towards 14 nanometer, many new features were added to the Liberty format to represent corresponding abstractions for design and analysis tools. Contributors to its upgrades included IC designers, EDA tool suppliers, and library developers.

Currently evolving under the IEEE’s Industry Standards & Technology Organization (IEEE-ISTO), the format continues to progress along with the technology it supports. Overseeing its evolution is the Liberty Technical Advisory Board (LTAB), a group of experts with a vested interest in maintaining the usefulness and robustness of the Liberty format.The group continues to tap into Synopsys’ – and others’ – expertise which is made readily available. Most recently, the group discussed and approved several new features to help model low-power cells, which are critical to the advancement and sales of mobile devices.

The collaborative effort among semiconductor foundries, fabless design houses, semiconductor IP providers, and EDA tool vendors (several in addition to Synopsys) is continuing to benefit the entire industry. It is also helping Synopsys maintain close ties with the entire semiconductor ecosystem to better understand upcoming requirements and challenges – giving us an opportunity to be the first to provide innovative solutions.

Technology leadership is a multi-faceted undertaking – one that requires continuous effort in several areas. One of these important areas is technical standards. It may or may not come as a surprise, but cooperating on and contributing to industry standards activities can further a company’s technical leadership.

At my company, we collaborate with a wide range of players in the industry on standards issues. This includes competitors, partners, and customers – typically in a Standards Development Organization (SDO) such as the IEEE Standards Association or Standards-Setting Organization (SSO) like Accellera.

Through such participation, we often find that our endeavors to solve our customers’ problems are exactly the same as our competitors’. In fact, at times, the customers who are participating in standards activities are asking us to solve the same problem as they ask the other EDA tool suppliers. In many cases, standards-based collaborative efforts are far more efficient overall than having one vendor working directly with each customer.

The Universal Verification Methodology (UVM) and Unified Power Format (UPF) under Accellera (which is now IEEE Std. 1801) are great examples of standards helping solve much larger problems across the broad industry than what individual companies could do on their own.

These standards successes (and many others) led with technology donations from Synopsys, such as the core of SystemVerilog, the register package in UVM, and several low-power technologies for UPF. Donation (in standards parlance, “contribution”, to differentiate it from money) of production-proven technologies helps align the EDA  tool developers and IP providers with the customers in the most effective and expedient manner. As customers and non-customers become aware of the public standards based on our technology, not only does it continue to build Synopsys’ technical leadership and respect for our technologists, but it also provides the opportunity for adoption of our tools and methodologies because they are standards-compliant. This is yet another good reason why we at Synopsys continue to be actively involved in standards activities.

An analogy of “three big dogs hovering over a bowl of dog food” has been used to explain the business challenges of the EDA industry. This oft-cited quote is attributed to Cadence’s founder and first CEO, Mr. Joe Costello, debating how EDA had become a fixed-pie industry on a panel at DAC in 1995. For history buffs, amusingly, the response from Synopsys’ CEO – then and now – Dr. Aart de Geus, was “If you think of yourself as a dog, you only deserve dog food!” Surely, the quote was highlighted out of context; but it leaves one with the nagging question of how does an industry go about growing the pie rather than redistributing the fixed pie? Of course, there are many well-proven business strategies for doing so, and standards is certainly one of them.

An ecosystem built around technologies that are based on support for industry standards has many advantages. Even while pointing to Apple’s success through a strategy of controlling the entire ecosystem, one must realize that all those consumer devices connect through well-known standards such as Wi-Fi (IEEE 802.11n) and USB, and the iPhone connects through different phone carriers. It will also be interesting to watch whether Android can topple Apple again like the IBM PC compatibles did decades ago.

The point is that standards – specifically, standards-based interoperability – enable two or more industries/industry segments to interact with each other to provide a desired and complete solution, thereby growing and benefiting each of the industries.

However, the mere creation or existence of a standard does not by itself grow the market. In fact, until it is widely adopted, it is difficult to say whether there is actually a standard or not. To produce an actual standard, adoption of the standard needs to be shepherded through product introductions, education, books, conferences, white papers, and so on. It’s also necessary to nurture new business models, forge partnerships, and continue on an evolutionary roadmap for a period of time before it becomes apparent that the use of certain technology has become a standard. The length of this time varies by industry and degree of difficulty to implement the standard, and in the EDA industry it is usually at least 2 years.

A good example of an EDA standard that grew the pie is SystemVerilog. Based on contributed technologies, it took (arguably) about 3 years to complete and have serious adoption begin. At present, there are at least 125 products, solutions, and training offerings that make up the SystemVerilog-enabled market.

Feeding more dogs with a bigger pie makes everyone – suppliers, customers, and investors – happier.

It’s been never-ending excitement in the standards game since September 2007 when this blog began. After nearly 4 years, it’s time for a short vacation from blogging. I’m certainly not leaving the standards arena. Instead, I’ll likely be doing even more with the IEEE Standards Association. I’m also starting to work with people who are entering the world of standards and are looking for advice and guidance.

I”ll be around in many places. Listen as I host interesting guests on Conversation Central. Follow me on Twitter. See what we’re up to on Synopsys’ Facebook page. Connect with me on LinkedIn.

In the Fall, I promise I’ll be back. There will be interesting standards topics to write about. Hint: IEEE 1801 (UPF) and CPF.

Have a great summer, everyone!

I’m not sure what evolves faster, semiconductor technology or social media. One thing is certain – they both change quite rapidly. In the Electronic Design Automation industry, Twitter has caught on over the past two years or so. (Moore’s Law-ish?)

One of the most valuable aspects of Twitter is that millions of people are constantly posting information (or misinformation or non-information). All that information is searchable. Twitter users can make their posts easier to find by including a “hashtag” in them. A hashtag is simply a keyword, preceded with the hash symbol (#), that identifies the post as being related to a specific topic.

As more of us began talking about EDA on Twitter, and as we became experienced users of this interesting communication channel, we began including a unique hashtag in our posts (tweets). We chose the obvious, #EDA. Life in Twitterville was good, and we could find conversations about EDA easily.

Recently, people noticed that #EDA was being used in tweets that had nothing to do with Electronic Design Automation. They showed me tweets about the Economic Development Act of 1965, a book about psychology by a person whose first name is Eda, and countless tweets written in different,  non-English languages (I’d print them, but I don’t know what they say; I *do* know they’re not about designing chips).

#EDA had finally become too diluted for several of us in Electronic Design Automation to be useful anymore. (If you’d like to see the dilution, type #EDA into the box at search.twitter.com.) A popular and respected marketing consultant, Daniel Payne (@marketingeda), asked me for help in establishing a new hashtag for the EDA industry. He suggested #SemiEDA, and I agreed that it would be unique and readily associated with our industry. A quick search of Twitter showed that no one was using it.

We started to spread the word that #SemiEDA is a good replacement for #EDA. I expected it would take a while for #SemiEDA to become a standard hashtag that most everyone in EDA would adopt. I’ve been quite surprised, however, to see how fast it’s being embraced. Less than 24 hours after I tweeted “Announcing a new hashtag…”, more than 30 posts had been made that potentially reached 3,600 people!

At the time of this blog post, #SemiEDA is being adopted by more and EDA Twitter users. And their posts are quickly discoverable, unlike those now buried in search results for #EDA.

As the momentum of #SemiEDA builds, we’re continuing to include #EDA in tweets along with #SemiEDA. This can help guide people to the new hashtag in a much less disruptive way than immediately abandoning #EDA.

So welcome to the new standard for Electronic Design Automation on Twitter – #SemiEDA.

BTW, in doing research for this article, I wondered when I first started using Twitter. It was December 19th, 2008. I did not begin with the standard, “I just signed up for Twitter”.

Two of my (many) passions are Twitter and standards. Recently, I completed a fun project that combined both. But in an old-fashioned way. The publisher of the THINKaha book series encouraged me to write a book for their “#XYZ tweet” collection. Each of these short books contain 140 bite-sized ideas on a topic that lets the reader get a quick taste of the subject and/or the author.

I agreed, and the” #STANDARDS tweet” book was born. Tweets in print are rather odd, but it was a fun experience. Thanks again to Rick Jamison (@rickjamison), there are some clever cartoons that adorn the text. Also, thanks to JL Gray (@jlgray) for writing the Foreword and supplying the funniest headshot I’ve ever seen. Too bad I couldn’t bring myself to use it – instead, the book has JL’s officially nice face in the front matter.

If you’d like a free copy of this little book, post a comment, send me an email, connect with me on LinkedIn, message me on  Facebook, or tweet an @mention or DM, and I’ll put one in the mail for you.

Happy Tweeting and Happy Standardization!

@karenbartleson