Archive for the '3. Duh.' Category

There comes a time in any writer’s life when she or he just can’t write. The well-known phenomenon of
“writer’s block” plaques professional authors, college students, and thank-you-note-writing-kids alike. Today, I have a bad case of it.

I wanted to write about something interesting. Posts about the WiMAX vs. LTE standards war, “The Web is Dead” from Wired magazine, and legal issues in social networking are sitting in my drafts folder, unformed and uninteresting.

One of my colleagues (“Rick Jamison of “The Listening Post” blog) compiled a list of resources that you might find helpful the next time writer’s block strikes you. Here they are. I’m going to read them.

Ten Ways to Cure Writers Block

How to Cure Writer’s Block

Writer’s Block: Is It All in Your Head?

How to Cure Writer’s Block – Eleven Tips

6 tips to cure writer’s block

How to Cure Writer’s Block

36 Ways To Cure Writer’s Block

Writer’s Block/ Writer’s Anxiety

Easy Ways to Stop Writer’s Block

Today’s economic climate is challenging to everyone, needless to say. Purchase decisions are scrutinized and budgets are tight for customers and suppliers alike. Now, as always, customers want choices and complete solutions. Interoperability – and suppliers’ programs that promote it – are now as important to customers as ever.

My company continues to be a long-time champion for interoperability. Please indulge me while I brag a little. Recently, a respected industry analyst said that “Synopsys is the king of interoperability” (scroll down to the “S” catagory). I admit that I felt a bit of a glow when I read this.

At Synopsys, we continue to work hard and spend significant resources to provide interoperable products and solutions to our customers. Our flagship interoperability program, in-Sync, allows scores of EDA companies to develop and test interfaces to our key products. Our catalyst programs help institute new and advanced industry standards such as SystemVerilog. Our standards program proactively provides the industry with technology and resources to help bring about much-needed standards via formal committees and open source. Presently, we are members of more than 30 standards organizations, our employees participate in 60+ standards-setting committees, and our products support as many industry standards. And for the most sensitive interoperability challenges (legal situations, for instance), our S.U.R.F. program provides secure facilities for other companies to debug problems with interfaces to our tools.

Why do we keep investing in interoperability programs?  Simple. Our customers require it. While we would certainly enjoy being the sole supplier of EDA solutions on the planet, we recognize the realities of healthy businesses. Working with competitors to allow our customers to make their best choices brings a certain measure of health to our company.

Something I learned very early in my career is that an IC designer’s job is *not* to run CAD tools.  It’s to produce a circuit design. This requires many tools combined in specialized flows, which of course implies interoperability.  Interoperability doesn’t happen by itself, and I’m proud to be part of a company that understands and cares about it. I believe our customers appreciate it.

EDA standards blog The Standards Game
open open standards in-Sync TAP-in SURF Synopsys interoperability EDA standards EDA interoperability

In this week’s SCDSource article by Richard Goering, “Mentor, Cadence VMM support may boost VIP interoperability”, Cadence states they support VMM.  With all 3 of the big 3 EDA vendors (Cadence, Mentor, and Synopsys) supporting VMM, I think it’s safe to say that VMM is well-accepted in the industry.  ‘Nuff said.
EDA standards blog The Standards Game
VMM Verification Methodology Manual open verification methodology
VMM OVM open standards verification standards

It is with pleasure and a measure of pride that I’m letting everyone know that  Synopsys’ VMM verification methodology is now available via open source under Apache 2.0. We have heard numerous requests for our VMM implementation to be made open source, and today we have done just that.  And more.  VMM is as open as it gets.

In addition to the source code for our complete VMM implementation, we have also added a variety of resources to support everyone using or planning to use the VMM verification methodology.  All materials and resources are available now for free download at VMM Central including:

Source code for Synopsys’ complete implementation of VMM:

• VMM Standard Library
• VMM Register Abstraction Layer application
• VMM Reusable Environment Composition application
• VMM Memory Allocation Manager application
• VMM Hardware Abstraction Layer application
• VMM Data Stream Scoreboard application
• VMM Macro Library

Other resources to help improve productivity for both new and existing VMM users, such as:

• Documentation for the VMM Standard Library and VMM Applications
• VMM utilities, including RALGEN and VMMGEN, for rapid environment development
• Example VMM environments
• HVP verification planning language specification
• User papers and technical articles
• VMM user discussion forum
• “Verification Martial Arts” blog by Janick Bergeron, Synopsys fellow and co-author of the Verification Methodology Manual for SystemVerilog

I encourage everyone – customers, partners, and competitors alike – to visit VMM Central, download materials, and join the discussion group.

What does this mean to Accellera?  Simply that the donation we made to them of Synopsys’ VMM implementation is now available to everyone, inside and outside of Accellera.  While the Accellera technical subcommittee works on its formal standard(s) for verification IP interoperability, our customers, partners, and competitors can freely use and share VMM throughout the industry. 

It also means that portions of our original donation made to Accellera that were rejected by Mentor Graphics (which we were forced to remove) are now completely available to Accellera anyway.  Mentor Graphics has said they “can’t wait to get their copy of VMM”.  Now they can without any restrictions (and without complaints).

There are some unique aspects to VMM open source.  First, no registration is required to download the VMM implementation source code (unlike OVM).  Second, powerful utilities are available to augment the user’s deployment of VMM (unlike OVM).  Third, VMM has been used widely in industry on hundreds of projects by numerous customers and partners for years (unlike OVM).

Why is there any kind of license at all?  Because some companies don’t feel comfortable even looking at technology that was developed by someone else for fear of “pollution”, “tainting”, and other ominous perceived consequences.  (Which I think is silly – Synopsys donates technology, makes a public announcement, then somehow is going to file suit against users of the donation?  That doesn’t compute.)  The Apache 2.0 license is about the most flexible on planet earth.  It clearly spells out the rights given to anyone who accepts the license.  Among other things, users get the right to use VMM without restriction or requirement to report back to Synopsys, Accellera, or anyone else.  The only requirement is to keep the existing copyright statements in any VMM code that is not modified in a derivative work.

Speaking of derivative works, we have no intention of forking the VMM implementation away from the Accellera donation.  We will certainly stay closely involved in Accellera’s work – indeed, some of our top experts are active participants in the working group.  If there are future updates to VMM, the Accellera technical subcommittee will be able to obtain them immediately or at their scheduling discretion with no further ado.  

The VMM verification methodology is a structured approach to verifying complex system-on-chip electronic designs that significantly improves verification test coverage and minimizes the number of costly chip re-spins due to undetected functional errors while reducing test development time. By releasing the source code for the complete VMM verification methodology under the familiar Apache 2.0 open source licensing model, Synopsys is making this proven methodology easily accessible to verification engineers worldwide under simple, well-recognized terms.

Synopsys has again shown that we champion the cause of interoperability. From the Verification Methodology Manual book that anyone can buy, to our donation to the Accellera technical subcommittee which anyone can join, to open source via Apache 2.0, VMM is open.  Q.E.D.

EDA standards blog The Standards Game
verification methodology manual open verification methodology
VMM OVM open standard verification standard
open source open source standards Apache 2.0 Apache license

Hello, Everyone!  I had been wondering why none of my posts had received any ratings since the end of last year.  One of my subscribers recently pointed out that nothing was happening upon mousing-over (is that a word?) the stars.  I did a little investigation and found that an option had been incorrectly set which pretty much disabled the rating system for my blog.

 The system is now fixed, and I’m looking forward to more ratings from my friends at Cadence. 

There is chatter in the standards arena that unless the 3 biggest EDA vendors can agree at the outset, a standard cannot be successful.  What an innovative way to block standardization!

I cannot recall, in any organization, that there was agreement at the beginning of a standards effort.  Some disagreements were more heated than others, but all parties didn’t wake up one morning and say “Let’s be friends and make a standard.”  Yet, very useful and well-accepted standards were created. 

Let me give some examples:

SystemVerilog/’e’

SVA/PSL

Liberty/ALF

SDC/DCDL

Verilog/VHDL

UPF/CPF

Milkyway/OpenAccess

Blu-ray/HD (see, it’s not just EDA)

Sometimes, a single standard emerged.  Sometimes, there were two.  But it is undeniable that useful standards were introduced into and adopted by the market.  Of course, a single standard is best, but it is also undeniable that two standards are better than three or ten or a hundred.

So, I don’t believe that we must be in agreement before starting to produce valuable standards for electronic design.  If this were true, there would be no standards.

EDA standards blog
VMM OVM open standards verification standards
standards war verilog vhdl accellera edif ieee open source standards liberty openaccess
Unified Power Format UPF CPF IEEE standards IEEE P1801 low power standard

I was amused by a recent EETimes article written by my counterpart at Cadence. In the article, Stan Krolikoski states, “One of the ploys of many an EDA company releasing a technology is to call the technology ‘Open.’” He then proceeds to describe the “openness” of OVM.

I find it ironic that OVM was certainly not created in an open environment. Last year, EETimes ran an article about OVM entitled “Synopsys was not invited to join SystemVerilog OVM initiative”.

The article makes it clear that OVM was a closed initiative, cooked up by two of Synopsys’ competitors: “Responding to a question as to whether Mentor or Cadence had invited Synopsys to join the OVM initiative, Dennis Brophy, director of strategic business development at Mentor, said: ‘We did not.’”

OVM demonstrates that Stan is correct – “open” was a ploy from Cadence and Mentor. There’s nothing like the pot calling the kettle black.

(Translation of this idiom from Wikipedia: The phrase “Pot calling the kettle black” is an idiom, used to accuse another speaker of hypocrisy, in that the speaker disparages the subject in a way that could equally be applied to him or her. In former times cast iron pots and kettles were quickly blackened from the soot of the fire. If personified into animate objects, the pot would then be hypocritical to insult the kettle’s colour.)

EDA standards blog
VMM OVM open standards verification standards

I’ve been to a lot of standards meetings. More than I can count. Generally, the meetings have been civilized and the participants have been respectful. Yet, there have been occasions when tempers flared and adults behaved like children.

A few months ago, I observed a simple process for keeping a heated meeting under control. The process is used by the IEEE Standards Association Corporate Advisory Group, and I learned about it from their director of corporate programs.

I was impressed with the process because it:

- kept order
- minimized emotional arguing
- guided discussion to closure
- respected all participants

Affectionately called “When I See Your Hand” (or for acronym lovers, WISYH, although there’s nothing wishy-washy about it), the process is basically a FIFO queue – the first person with their hand up is the first to speak.

The Chair or meeting official is the discussion leader. The Secretary or other volunteer designee maintains a queue, watching for participants who raise their hand, recognizing them, and then recording their name at the bottom of the list.

As the discussion proceeds, the participants are allowed to speak when their name is read from the top of the list by the Secretary. After a person speaks, their name is crossed off the list and the next person is given a turn to talk. The Chair watches for and guides closure of a discussion thread while the Secretary keeps a watchful eye for raised hands.

The reason WISYH works is severalfold. The Chair can limit the amount of time each person is allowed to speak. Filibustering is not allowed to derail the meeting, and the speaker must make a point instead of babbling. The Chair can table tangent and off-topic discussions to return the main queue, or create a separate queue for future discussion. Because people must wait their turn, they have an opportunity to sort out their thoughts, calm down if necessary, and make a clearer statement when their time comes.

While I can’t say I’m looking forward to using WISYH, because that would mean a disorderly meeting, I can say that I have less dread of a heated standards meeting with WISYH standing by.

EDA standards blog

I must say I’m very much enjoying blogging about EDA standards. Not only is the topic interesting and important to my customers, but equally so to my competitors. In the short time that I’ve been blogging, I’ve received insightful comments, intriguing questions, and strongly-stated positions.

One thing I’ve really gotten a kick out of is some of the ratings. A creature named webwasher.Cadence.com has visited my blog and left behind but a single star. I think maybe it’s a compliment.

A rather strange survey is being conducted called “The Cost of Non-Convergence of Two Timing Model Formats (CCS and ECSM)”. Supposedly, its purpose is to ascertain the relative cost of supporting the two formats.

I can answer this question easily: it costs more to support two formats than one.

So, what is the point of using industry resources and time to conduct this survey? My fear is that it will be used to start a fight between the backers of the two formats. Let’s hope I’m mistaken.