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This year’s SNUG Silicon Valley is shaping up to be one of the best yet with another outstanding program in store for our customers. SNUG – the Synopsys Users Group conference – is Silicon Valley’s largest technical conference and one of Synopsys’ premier events. This year, it will take place at the Santa Clara Convention Center and kicks off Monday, March 26, 2012. I hope to see you there.

You might not realize that SNUG is Silicon Valley’s largest technical conference where the program is designed by engineers for engineers. SNUG provides users of Synopsys’ design tools and technology with an open forum where they can exchange ideas, discuss design challenges, and explore solutions. Today, there are 15 SNUG conferences worldwide that draw 9,000+ customers from more than 900 companies. For more information regarding future SNUG conferences, please refer to our World Wide Calendar on the SNUG website.

This year’s conference in Silicon Valley will feature more than 100 technical presentations as well as keynotes from leaders who are setting the tone for global design innovation. It’s also an opportunity for our customers to connect with Synopsys executives, our design ecosystem partners, and more than 2,000 members of the local design engineering community. Here is a preview of this year’s SNUG Conference-at-a-Glance.

SNUG Technical Chair John Busco, design Implementation manager at NVIDIA and one of the semiconductor & EDA industry’s first bloggers (here’s a link to his blog), will provide the opening welcome to the conference. He’ll introduce Aart de Geus, CEO & Chairman of the Board at Synopsys, who will deliver his keynote address, “Critical Mass, Systemic Complexity and Innovation: Catalysts for Designing Change.” John Cornish, ARM Executive Vice President and General Manager of ARM’s System Design Division, headlines Tuesday’s program with his keynote, “Partnering for Low Power,” where he will discuss next-generation process and the need for a system approach. Chenming Hu, Professor Emeritus at the University of California, Berkeley and former TSMC CTO, will deliver the technology keynote on Wednesday morning, “3D FinFET – New Structure Rejuvenates the Transistor!”

SNUG Silicon Valley keynote speakers: (from left) Aart de Geus, Synopsys, John Cornish, ARM, and Chenming Hu, University of California, Berkeley.

The technical program includes sessions related to low power, high performance, and embedded processor design, as well as design productivity and advanced design technology topics. In addition, the IP Summit, a special program designed for customers considering the use of IP to improve their productivity and design quality, will also be featured on Wednesday, March 28.

The Designer Community Expo (DCE) event will be returning to SNUG Silicon Valley as well. I particularly like this event because it grew out of an interoperability event that my team created. DCE is a unique opportunity for customers to meet Synopsys technology experts and our design community partners from across the electronics industry. Customers will be able to visit seven different design communities and see how more than 60 ecosystem partners are working with Synopsys to solve common design challenges.

If you are a Synopsys customer and wish to attend SNUG Silicon Valley, you will need to register on-site if you have not already registered.

I hope you enjoy another great SNUG in Silicon Valley.

We are celebrating our 25th anniversary at Synopsys. You’ll see “25 years of enabling innovation” throughout this year. As part of recognizing our anniversary, we’re holding a trivia contest which will continue through December 2012. No doubt there will be a standards question or two.

We’ll post a question – two each month – and the first person to post the correct answer will win a $40 Amazon gift card.

You can play two ways, on our Facebook page and through Twitter.

On our Facebook page:

• If you’re not already, become a fan (click “Like” on www.facebook.com/synopsys)
• Watch your Facebook feed for our trivia questions to be posted
• Post your answer in the comment area under the trivia question

Through Twitter:

• If you’re not already, follow us on Twitter (click “Follow” on www.twitter.com/synopsys)
• Watch your Twitter timeline for trivia questions posted by @synopsys
• Tweet your answer to @synopsys

The winner of each question will be announced right away via Facebook and Twitter.

Read the full contest rules here.

The contest is underway. The first question was, “What was Synopsys’ original name when the company was founded?” The answer is, “Optimal Solutions”. (Did you know that?)

For more trivia about Synopsys and our history, visit our timeline.

Play and enjoy the game! (Almost forgot, no Synopsys employees, please.)

We have a great lineup of guests for you on Conversation Central at the 48th Design Automation Conference. Join us in the audience in the front of Synopsys’ main booth to see the shows and talk with the guests. If you’re not at DAC, you can watch the video sessions live-streamed to our Facebook page. See the schedule below.

Dubbed “The Voices of DAC”, all shows will be recorded and published afterward for listening and viewing at your convenience. You can find the shows on iTunes (or search the iTunes store for “Conversation Central”) and on our show notes site www.synopsys.com/blogs/conversationcentral. Additionally, video Conversation Central shows can be seen on Synopsys’ Facebook page www.facebook.com/SynopsysInc and Synopsys’ YouTube channel www.youtube.com/synopsystv.

In addition to Conversation Central, we’ll give you a unique networking card with a QR code for your LinkedIn profile. Use your card to connect with colleagues and friends during the cocktail receptions on Monday, Tuesday and Wednesday from 6 to 7pm on the Garden Terrace on level 2 of the San Diego Convention Center. Continue using your card to connect with people throughout DAC and afterward.

If you’re a fan of Twitter or would like to experiment with it, come play our Twitter Trivia game. There will be two ways to win:

- Pick up a game card in Synopsys’ booth and find secrets to tweet at special DAC events.

- Tweet @synopsys and/or tag tweets with #snps from June 5 through June 9. Be sure to include #48DAC in your tweets. That way, you can win even if you’re not at DAC!

Come to Synopsys’ booth anytime to get a free copy of the newest book from Synopsys Press, “Social Media Geek-to-Geek: Practical Insights for Technology Marketers”. The author, Kathy Schmidt Jamison, will sign your book on Monday at 4:30, Tuesday at 11:30, and Wednesday at 10:30.

Conversation Central schedule for the 48th DAC:

The 48th Design Automation Conference is almost here. Again, there will be several activities of interest for both those of you who want to learn about standards and those who regularly play the standards game.

Standards are very important to EDA and semiconductor design industry. For 12^th year, Synopsys is organizing The Standards Booth (#3328) at DAC where you will find Synopsys along with its partners demonstrating interoperable flows using industry standards. The four pods represent widely used standards from Accellera, IEEE, OSCI, IPL, and IEEE-ISTO. The Standards Booth will be located right next to Synopsys main booth, so it will be easy to find.

Of course, it won’t be only standards and interoperability talk in The Standards Booth. We’ll make this a lot of fun with “Prize Frenzy” where every half hour we’ll have a drawing for an iPod Nano. A different color iPod Nano every day. That’s a lot of Nanos. (Or is it Nanoes?) To win one of them, come to the booth and collect your game card. Visit all four pods in the booth, fill out a short questionnaire (really short), and you are on your way to all the excitement of the prize drawing – every half hour, enter as many times as you wish. How cool is that?

On Wednesday morning, come to Marriott (Marina Ballroom F) and attend Synopsys’ Interoperability Breakfast: “On Safari with Custom Design Interoperability & Interconnect Modeling Standards.” Listen to leading users talk about their experience with use of interoperable PDKs (iPDKs) and Interconnect Technology Format (ITF). We’ll also announce the recipient of this year’s Tenzing Norgay Interoperability Achievement Award.

I will be right next door, in Synopsys’ main booth, if you’d like to stop by and say hello. We’ll have “Meet the Bloggers” periodically in the Conversation Central area – left front corner as you face the booth.

To get you in the mood for The Standards Booth, listen to the theme song from the first ever Standards Booth, “My Flow’s in Jeopardy”.

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Nominations are now open for the 2011 Tenzing Norgay Interoperability Achievement Award. You can nominate a friend, competitor, or yourself. The last day for nominations will be April 15, 2011 so don’t delay.

The annual Tenzing Norgay Interoperability Achievement Award, now in its eleventh (!) year, is presented to companies, organizations, universities, or individuals whose work:

¡ Surpassed common levels of interoperability

¡ Contributed to overall industry advancement

¡ Provided a new view of the future

¡ Ensured customer success

The award was named for the crucial role that Sherpa, Tenzing Norgay, played in the first successful attempt to reach the summit of Mount Everest in 1953. Many people think of Sir Edmund Hillary when they think of a Mount Everest hero. Yet without his faithful Sherpa by his side, Hillary might not have made it to such great heights. Likewise, those who work tirelessly to bring necessary standards and interoperability to industry are often overlooked. The Interoperability Achievement Award recognizes these achievements that are critical to a designer’s success.

To submit a nomination and see past winners, please visit the Tenzing Norgay nomination webpage here.

The award will be presented at the Synopsys Interoperability Breakfast event on Wednesday, June 8, 2011 at the Design Automation Conference in San Diego, CA.

But please don’t nominate me. I already receive plenty of kudos. (Thanks, KC Leung!)

There is more and more talk about the need for standards and interoperability in 3D. We mean 3D ICs – stacking chips in a single package – not to be confused with 3D entertainment which also is looking at creating standards such as those for 3D glasses.

And there is more and more action being taken. Several standards organizations have formed groups to study and/or develop standards for 3D ICs. These include: JEDEC, SEMI, SEMATECH, SIA, SRC, IEEE-SA, IEEE-ISTO, GSA, and Si2. It’s not surprising for a new technology to receive a lot of attention from the standards arena. There are technological and business challenges to overcome that can be helped by the introduction of appropriate standards. As the working groups sort out what’s needed, who will do what, where competition and cooperation should exist, and which standards will be adopted over others, there could be (OK, there likely will be) the usual turbulence that accompanies all standardization journeys.

The topic of 3D IC standards will be one of the discussions that will happen at the 18th Electronic Design Process Symposium (EDPS). The April 7-8, 2011 symposium will be sponsored by three of IEEE’s subgroups: Computer Society of Silicon Valley, Council on Electronic Design Automation, and Design Automation Technical Committee.

I’ve attended EDPS in the past and found it to be especially interesting because of its small, intimate nature. Presenters and attendees are there because they are passionate about their topics. If you’re interested in 3D ICs, you might find value in spending a day in Monterey CA discussing your views and asking questions of other participants.

Other topics at EDPS will include:

• Parallel EDA
• High-Level Design – including Requirements-Driven Design Flows
• Cloud computing – including Software as a Service
• Low-Power Design – with Solution Mapping to 2009 ITRS Roadmap

To see the program schedule and more information: www.eda.org/edps

To register directly: http://edps2011.eventbrite.com

The topic of 3D IC standards is likely to step to the forefront of the standards game in the coming year or two. Fasten your seatbelt.

The quite successful 2011 Design and Verification Conference was held last week. The most prominent topic at the conference was the Universal Verification Methodology, UVM, which is the latest standard ratified by Accellera. Instead of telling you about UVM myself, I decided to get information straight from one of the participants in the UVM effort, my colleague Yatin Trivedi.

Yatin told me, “The design verification community is rejoicing over the release of UVM 1.0. At DVCon 2011, the exuberance was quite visible. Let me just cite a few data points for any skeptic who might rush to call it “irrational exuberance” of Alan Greenspan fame –

- record number of attendees (more than 200) packed the all-day UVM tutorial

- standing room audience at Town Hall lunch meeting to talk about UVM and SystemC interactions

- full-house UVM panel that had six of the leading contributors answer Cliff Cummings’ tough questions

- 12 of the 37 papers were about UVM

- best paper awarded to Adam Erickson on “evil” UVM macros!

- more than half the exhibitors showed their support for UVM

- “Meet the Experts” in Accellera’s booth was a great place for attendees to interact with, who else?, the UVM Experts

- numerous tweets with the hashtag #uvm, and a number of blog posts about UVM

- … and who can forget the rousing applause as each contributor was recognized for their dedication?

“Yes, UVM was the biggest story at DVCon 2011. So, naturally, the question arises – what is UVM?

“UVM stands for Universal Verification Methodology. It is a verification methodology, based on a class library defined using syntax and semantics of IEEE Standard 1800, also known as the SystemVerilog hardware description language. Thus it is a SystemVerilog-based verification methodology, not a new language. The standard is defined by the UVM 1.0 Class Reference document approved by the Accellera Board of Directors.

“UVM is a fine example of ‘a standard developed by committee’. Accellera’s VIP-TSC not only worked on the standard – the Class Reference Guide document – but it went one step beyond to provide a Reference Implementation for the documented classes.”

I asked Yatin if the UVM effort followed any of The Ten Commandments for Effective Standards. He told me, “This industry-wide effort under Accellera demonstrates several commandments from the Ten Commandments of the Effective Standards:

- Collaborate on Standards, Compete on Products: Not only major EDA vendors participated in this effort, but several users from competing companies collaborated too (notably, AMD, Cisco, Freescale, and Intel). Clearly, everyone was working towards the same goal.

- Start with Contributions, not from Scratch: UVM is built on top of the Base Class Library (BCL) of OVM, widely-used contributed technology such as VMM’s Register Abstraction Layer (RAL) and phasing mechanism, support for Open SystemC Initiative’s (OSCI) Transaction Level Modeling-2.0 (TLM-2.0), and the committee-developed Command Line Interface and Resource Manager.

- Be Truly Open: All Accellera standards are open to anyone who wants to develop and use them. They are also free. In case of UVM, the Reference Implementation is also open and available at no cost. Many leading EDA vendors have verified that the reference implementation is usable on their tools. The reference implementation is an Open Source project, so the support is provided by the community.”

Accellera’s VIP-TSC working group will continue to seek ways to improve the UVM standard and enhance the reference implementation. If you wish to contribute, please join the VIP-TSC.

The Design and Verification Conference (DVCon) starts on Monday, February 28, 2011. This year there are some exciting new additions that I’d like to highlight for you. (And encourage you to attend – yes, I’m the General Chair of DVCon this year.)

The usual high-quality technical program will remain the center of gravity for DVCon. Technical Program Chair, Ambar Sarkar, gave us a behind-the-scenes view on Conversation Central last week (listen here). There were so many valuable abstracts submitted and not enough time slots to accommodate them all, that we added 2 poster sessions on Tuesday to expose you to important information you wouldn’t get otherwise.

UVM – the Universal Verification Methodology which is the newest standard ratified by Accellera – will be featured in tutorials, technical sessions, and 1 of the 2 panels at DVCon. You’ll learn what UVM is and how to deploy it for your complex designs.

In the technical sessions, you’ll also gain worthwhile knowledge of advancements in modern design and verification including SystemVerilog, low power, mixed-signal, TLM-2, and a variety of techniques and approaches to attaining the best design verification possible.

A unique feature of DVCon is that the attendees get to choose the Best Paper. This year, the voting will be done online (hooray – no more paper ballots to tally). You can use your mobile device, laptop, or the computers provided at the show to vote during or at the end of the conference. I’ll have the honor of announcing the winner on Wednesday at 5:00pm.

UPDATE 2/25/11: The time of the reception is 5-7:00.

As a special event, Qualcomm will host a reception on Monday night from 6-7:30 or 8:00 in the Donner Ballroom located in the Doubletree Hotel. They will give a short presentation on verification methodology by Qualcomm staff, and they will provide hors d’oeuvres and drinks. One lucky attendee will walk away with an un-tethered HTC Evo 4G. Best of all, Qualcomm is there with recruiting in mind. (Personally, I’m delighted by this. Recruiting is the nicest word I’ve heard in a long time.)

UPDATE 2/25/11: Here’s the link to Qualcomm’s Design and Verification opportunities.

The Industry Leaders panel on Wednesday is called “Making Great Products Great”, and the panelists will talk about some amazing products and how they made them great. (I”m really looking forward to hearing about fixing the Hubble Space Telescope.)

The keynote speech this year will be delivered by Wally Rhines, Chairman and CEO of Mentor Graphics. It’s always interesting to listen to Wally and hear his insights into our amazing (crazy) industry.

One of the things people told us in last year’s DVCon attendee survey was that they wanted more vendors in the exhibits. We are delighted to announce that there will be twice the number of exhibitors at DVCon this year compared to last year, and 14 will be there for the first time.

NASCUG – the North America SystemC Users Group – is co-locating again with DVCon on Monday. “SystemC Day” will feature the ever-charming Jim Hogan as the keynote speaker.

If you can’t make it to the entire show, the free exhibits-only registration will give you:

• Access to exhibit hall on Tuesday, 2:00 – 6:30pm, and Wednesday, 2:00 – 6:30pm
• Tuesday Keynote at 4:00pm
• Access to the Tuesday Panel at 2:00pm and the Wednesday Panel at 3:45pm.
• Eligibility to register for the tutorials on Monday or Thursday. Each tutorial is $75.
  Maximum of three may be selected

I’d like to thank DVCon’s sponsor, Accellera, and the conference management, MP Associates, for again producing this significant event. Details and registration can be found on the DVCon website. Hope to see you there!

On Sunday, December 5, 2010, the IEEE Standards Association held their annual Awards Ceremony. The event was again most enjoyable with good friends, esteemed colleagues, good food, musical entertainment, beautiful flower arrangements, and the ever-popular duet of Judy Gorman (IEEE-SA Managing Director) and Mary Lynne Nielsen (Director of the IEEE-SA’s Corporate Program). At the heart of the occasion was, of course, the awards.

I’d like to highlight two of the IEEE-SA awards as they pertain directly to the technical standards work I’ve been involved in – design automation. The first is the Ron Waxman Design Automation Standards Committee Meritorious Service Award. It was presented to Dr. Hal Carter, Professor Emeritus at the University of Cincinnati. Hal was a founding member of the DASC (along with Ron Waxman) and has contributed broadly to the advancement of electronic design. The gentleman in the photo below are (from left to right) Ron Waxman, Chuck Adams (President of the IEEE-SA), Hal Carter, and Ted Olsen (Chair of the IEEE-SA Awards Committee).

The second award is the IEEE-SA Corporate Award which is given to companies that provide outstanding leadership and contributions to IEEE standards. The big grin is on my face below (that’s Rich Goldman on the left, Yatin Trivedi on the right) because Synopsys received the award! For many years, our employees – past and present – have worked hard to further IEEE standards, and the award belongs to a whole team of people.

I would be remiss if I didn’t mention that the IEEE-SA Corporate Award was also presented to Underwriters Laboratories (you see their logo everywhere) for their commitment to safety standards that affect everyone’s daily lives.

Congratulations to all of this year’s IEEE-SA award recipients and those who helped make them successful!

In case you missed the 23rd EDA Interoperability Forum, here are some brief highlights. We will make the presentations available on the Forum website on October 30. The turnout was quite good. Thanks to all the presenters and attendees for participating. Thanks also, to Oracle for providing their beautiful auditorium at their Agnews Center.

I was the MC for this event and I did enjoy myself – plus learned some new things. In the opening remarks, I reminded everyone of this year’s Tenzing Norgay Interoperability Achievement award, the IEEE-ISTO, for their work with the Interconnect Modeling Technical Advisory Board and the Liberty Technical Advisory Board. We gave away copies of my book, The Ten Commandments for Effective Standards, and had drawings for iPod Nanos.

Conversation Central was broadcast live from the stage of the Forum. Show notes (along with the recording) are available now. If you’ve subscribed to Conversation Central via iTunes, the podcast will magically appear shortly.

Additional program highlights:

Jingwen Yuan provided the latest information about the IPL Alliance. The IPL 1.0 download package is now available. A noteworthy next step for the IPL Alliance is to collaborate with Si2’s OpenPDK  effort to avoid ,multiple standards for PDKs. The Alliance will continue to maintain and improve IPL1.0, work on standards for analog constraints, educate the industry, and grow the IPL Alliance (STMicroelectronics just joined), TSMC, TowerJazz, LFoundry, STARC have developed foundry iPDKs and multiple EDA tools support the iPDK standard – the Alliance’s efforts are paying off.

The IPL Alliance has a LinkedIn group called “IPL & iPDK”. This is a good place to connect with the more than 200 members.

Rich Morse (SpringSoft), who chairs the IPL Alliance design constraints working group, told the audience about his group’s efforts towards interoperable constraints for analog design. Today, there is no open, common standard in this space, and this group has a lot of good work ahead of them. They’ve defined a roadmap to tackle this one step at a time. Their goal is to be able to show early demos at DAC 2011. They definitely would appreciate donations! Technology, I mean, but I’m sure they’d take cash, too.

Yatin Trivedi (Synopsys) gave an update on standards from Accellera, IEEE-SA, OSCI, and some de facto standards as well. He reminded everyone that the end goal of standards is productivity – enabling the exchange of information in a long chain of tools and methodologies. Music to some ears (mine included) was hearing that Si2 has joined the IEEE P1801 (UPF) working group. Remember CPF and UPF, the two formats for describing low power design intent? The P1801 working group will now start reviewing where the two formats differ and propose a interoperable solution. There’s no clear schedule or plan yet, but this is definitely a step in the right direction.

Frank Schirrmeister (Synopsys) presented interesting data on the ROI of system-level design. Be sure to get his presentation to see the full report. He also described important cost reduction opportunities for system-level: design cost reductions, start software development early, augmentation with hardware based prototyping, and use virtual development kits. He said the system-level market is still young and there is a lot of opportunity.

Will Straus (Forward Concepts) presented his expert analyst’s view of the wireless market. It’s so big, it rivals the PC market. The market for cell phone components is $50B (!) with the LCD being the most costly of the components. He gave us insights into the components of smart phones and what’s coming in the future – the “Frankenphone” as he affectionately called it.

Will then led a session and panel of speakers with: Jose Corleto (Qualcomm), John Goodenough (ARM), Grant Martin (Tensilica), and Johannes Stahl (Synopsys). They talked about today’s changes and challenges in wireless from their different perspectives. And of course, the need for interoperability.

Janick Bergeron (Synopsys) provided good technical insights into register package interoperability for verifying complex system designs. He, along with Mark Glasser (Mentor) and Richard Weber (Semifore), helped answer register package questions and provided information about how to use UVM.

Overall, this was a successful Interoperability Forum and many people walked away with flowers (from the tables) as well as knowledge.