Archive for February, 2010

DVCon 2010 starts this Monday, February 22, at the Doubletree Hotel in San Jose, CA. So far, the numbers are up over last year, and we’re expecting a good crowd.

To date, 483 attendees have registered, while last year at this time there were 475.

In addition, the number of papers submitted was greater than last year, and we added an extra day to accommodate more tutorials.

Don’t let the floor plan fool you – the diagram is deceiving. In 2010, there will be 26 exhibitors, one more than in 2009.

Watch for DVCon-related tweets by searching for the hashtag, #dvcon. Find blogs posts, articles, photos, and videos by Googling dvcon.

See you at DVCon!

The Accellera standards organization has been in existence for 10 years now. I remember like it was yesterday when the boards of directors of Open Verilog International (OVI) and VHDL International (VI)decided that merging the two organizations made sense for the industry. The “standards war” between Verilog and VHDL had ceased to be interesting, and the two hardware description languages were coexisting fairly peacefully. Forming a single organization to oversee the development and adoption of standards for language-based design of integrated circuits made a lot of sense.

The merged organization was named Accellera, and it brought efficiency and focus to standards development in the design automation industry. (Some people thought the name sounded like a car or a vegetable, but I thought it had a nice ring. Gabe Moretti tells the naming story on his blog.)

Several of us had been representatives on both of the OVI and VI boards, so it was a relief to attend half the number of meetings while accomplishing the same amount of – or even more – work towards providing standards for the industry. I recall one day going to a VI board meeting in the morning where people said, “Oh, those Verilog guys…” and then going to an OVI board meeting in the afternoon where people said, “Oh, those VHDL guys…” I kept thinking since “those guys” are “us guys” it sure would be nice to have just one board.

Over the past decade, Accellera has had many successes. Obviously, they have provided numerous market-relevant, well-adopted standards for improving the chip design process. Two of my favorites are SystemVerilog and the Unified Power Format (UPF), both of which are now IEEE standard 1800 and 1801, respectively.

SystemVerilog’s widespread adoption is witness to its success.Starting out with technical donations from Accellera member companies BlueSpec, Mentor Graphics, Motorola, Novas, Real Intent, and Synopsys – with additional contributions from user companies – SystemVerilog expanded upon the long-time industry standard language, Verilog, to address modern design challenges.

Speaking of SystemVerilog and the IEEE, another noteworthy accomplishment of Accellera is the key role it played in supporting the IEEE Standards Association as it established its corporate standards program. SystemVerilog was the second standard to go through the entity-based (one company, one vote) standardization process of the IEEE. It helped pave the way for about 20 corporate standards projects that have been completed or are currently underway in the IEEE.

One of these corporate standards is 1801, which began in the IEEE when Accellera transferred its UPF standard to them. UPF was developed in record time – less than 6 months from the official start of the working group – and arguably, at a reasonable cost to the industry. I was part of the Accellera working group that produced UPF. When it was finished, I made some rough calculations to estimate how much the companies had paid for their employees to develop UPF. For the 9 month period from concept to completion, I counted the number of people in the group, estimated how much of their work week they spent on the standard’s creation, and included an approximation of how much time employees of two standards organizations (Accellera and Si2) spent discussing the landscape for UPF. Not scientific, but interesting anyway, my guesstimate was that 7.3 man-years were invested by the UPF working group. Using a fully-burdened hourly rate of $200, the total cost would have been about $3M. Contrast this to the estimate of 100 man-years (see the last paragraph of the article) that were spent developing the Common Power Format (CPF). That would have been a cost of over $41M! These figures may have been greatly under- or overestimated, but to me it shows the value of cooperation among competitors when producing an industry standard.

Accellera is going to celebrate its 10th birthday with a lunchtime event at DVCon on Tuesday, February 23. I hope you join me in wishing Accellera many more decades of success.

One of my favorite conferences is EDP – Electronic Design Processes. The 17th EDP symposium will be held on April 8-9 2010. As always, the venue is the Monterey Beach Hotel in beautiful Monterey CA. What I like about EDP is its intimacy and sharing of ideas about how chip design can be done better and where technology might be headed. Participants are industry veterans, company leaders, respected academics, and regular people like me who just soak it in. During the presentations, conversations start up and debates can result. Unlike presentations at large conferences which can be mostly one-way communication, EDP’s talks engage the audience.

There’s still room in the program for some good talks, so if you’d like to present an interesting topic, the organizers want to hear from you. They welcome presentations on a wide range of subjects – but no product commercials, please. The submission deadline is February 26.

This year there will be an emphasis on multi-processing (especially for, but not limited to, EDA) and on 3D ICs. There will be a power(ful) panel too, but at this point, EDP organizers see multi-processing as “hotter” than power. Other topics may include cloud computing, DFM, and the analog revolution (is there one?).

A special part of EDP is the beach walks. There’s nothing like a refreshing walk with stimulating conversations among friends. It was during one of these walks that a colleague convinced me that global warming is real.

EDP is sponsored by the IEEE’s Computer Society and Design Automation Technical Committee. Early registration ends March 1, so if you like valuable workshops and like to save money, sign up this month.

The annual San Jose Synopsys Users’ Group will be held at the Santa Clara Convention Center on March 29-31. The technical program committee is chaired this year by John Busco of NVIDIA (he has a great blog, by the way), and it’s sure to be first-class.

The social media tag for everyone to use is “snugsj10”. Whether you’re posting a blog entry, writing a news article, or sending a tweet, please use the tag to make your content easy to find. Synopsys users who can’t attend SNUG will either appreciate it or be envious – maybe both.

The traditional Tuesday night interoperability event will be unlike any you’ve seen before. I’ll be very interested to hear what you think about it. Along with the always popular prize booth and food (yes, I’m told there *will* be shrimp), you’ll be able to meet Synopsys bloggers in their respective design communities. We’re putting a lot of effort into this occasion, and we think it will be a worthwhile experience.

If you’ll attend SNUG, be sure to say hi to me. I always enjoy meeting my customers.

DVCon 2010 is coming soon –  it starts on Monday, February 22, at the Doubletree Hotel in San Jose CA. DVCon, the Design and Verification Conference, continues to bring valuable information to chip design engineers about modern techniques and industry standards which help them in their day-to-day efforts.

What’s new with DVCon this year? To begin with, it’s one day longer. There were enough high-quality tutorials proposed that the steering committee decided to extend the conference to accommodate them.

The panel that was previously known as the “big-wigs” or “troublemaker’s” panel will take a new approach and focus on real world problems being faced today. Called “What Keeps You Up At Night?”, it will give chief technologists the opportunity to talk about their challenges with contemporary chip design. (You’ll notice there are no EDA companies represented in the lineup of panelists.) The moderator will be JL Gray, a fellow blogger and the author of Cool Verification.

For the first time, the DVCon 2010 Steering Committee included a Social Media Chair (yours truly). In addition to writing blog posts about the conference like several of us did at DVCon 2009, you can expect tweets, photos, videos, and articles. You’ll see the “Twitter Tower by Synopsys” at the conference where attendees can watch the live stream of tweets. If you can’t attend DVCon, fire up your TweetDeck for a personal-sized Twitter Tower.

My colleague, Rick Jamison, and I will host a session on Monday evening at 6pm that everyone is welcome to participate in. Our “Social Media 101 for Engineers” will be an informative (I hope) discussion about social media basics and how today’s new media can help you get your work done better and manage the ever-increasing amount of information that’s out there on Web 2.0. We don’t want to just do a presentation, we want to talk with you, so join us if you can.

As a reminder, everyone posting anything about DVCon is encouraged to use the tag, dvcon, for all blogs, pictures, videos, and articles; use the hashtag #dvcon for tweets. Searching for these tags can put interesting facts, news, and stories at anyone’s fingertips.

On Tuesday, Accellera – the sponsor of DVCon – will have a birthday party. At a lunchtime event, Accellera’s 10th year will be celebrated. I mean all their 10 years, not just the 10th.

Finally, NASCUG (the North America SystemC Users’ Group) will be co-located with DVCon. It’s a good opportunity for system-level designers to capitalize on two events in the same week.

See you at DVCon!

DesignCon 2010 is happening now. One of my fellow bloggers, Colin Warwick, put together a video spoof that I thought you might enjoy. First, a disclaimer: I’m not endorsing his product. Second, a proposal: I think we should standardize it. Third, a second thought: Never mind the standard – I rather like my job.

I’ll pass your comments on to Colin. He’ll probably get a kick out of your feedback.