I can hardly believe it. I’ve been in the EDA business since 1980 when I joined TI’s Design Automation Department after graduating from Cal Poly with my BSEE. Since 1995, much of my attention has been focused on EDA standards. I reached a moment of truth this year when I admitted, albeit reluctantly, that I could be called a standards-lifer. So, I decided it’s time to share my perspectives on what’s going on in the standards arena. Welcome to my blog - I can’t wait to hear from you! UVM: Collaboration for the Right Reasons
Posted by Karen B on January 14th, 2010
Congratulations to Accellera’s Verification IP Technical Subcommittee (VIP-TSC) for reaching yet another milestone on its journey to achieve harmony among verification standards. The near-unanimous desire and commitment to create a Universal Verification Methodology is an indication of the still growing need for collaboration among verification engineers, verification IP vendors, service providers, and tool suppliers – and their faith in Accellera to do so as an open standards organization.
In my October 1, 2009 blog post, A milestone completed towards verification standards, I wrote:
Now it’s time for the group to start working on their “long term” standard. Their efforts will produce a common base class library that can be used in simulators from multiple design automation tool vendors. The common base class library will foster a broad (universal) verification methodology to benefit verification engineers and developers of verification IP.
Again I’m optimistic that the VIP-TSC will provide the industry with an effective verification standard. Hmm. Maybe they will call it the Universal Verification Methodology (UVM).
According to the status report from the VIP-TSC, the next phase of their work is indeed called the Universal Verification Methodology (UVM)!! I’m pretty sure the working group didn’t refer to my post when deciding on a name for the standard, but it’s fun to see a prediction come true nevertheless.
And now it’s time for the group to start working on their “long term” standard. Their efforts will produce a common base class library that can be used in simulators from multiple electronic design automation tool vendors. The common base class library will foster a broad (universal) verification methodology to benefit verification engineers and developers of verification IP.
The VIP-TSC working group that will now tackle UVM appears to be focused on a critical aspect of standardization – delivering not only a specification but also a usable reference implementation. In the short-term phase of their work, they created an interoperability guide, and now they will work on providing a single UVM library that will reflect the best of VMM and OVM. This is what I like about an industry collaboration that’s focused as much on deployment of a standard as it is on the creation of it.
I’m glad to see this open, inclusive, and timely standard coming to life with support from a wide-ranging verification community. Synopsys strongly endorses this UVM effort under Accellera. I encourage the committee to ensure that UVM not only meets immediate requirements but also builds the foundation of an industry-wide verification methodology for years to come.
Overall, big kudos to the working group for their focus on the long term goals, their dedication, and their hard work. It’s a great way to start 2010!
RSS
The VIP-TSC status by Tom Alsop, VIP-TSC co-Chair, is available at http://www.accellera.org/activities/vip/VIP-TC_standard_effort_update_Jan_2010.pdf
When I gave my recommendations to the subcommittee I called my presentation “Suggestions for UVM”. A minute or two into the live presentation someone corrected me – he said that I should call it CBCL (Common Base Class Library), not UVM.
I thought to myself – “Well, UVM is such a better name for this…”.
Glad to see the subcommittee changed it back to UVM
Karen, nice endorsement of an Accellera group that’s been working hard to drive industry standardization of methodology. Cadence of course has also been very active in the VIP-TSC and has devoted a lot of resources to help it be successful.
However, I couldn’t help noticing that you didn’t mention how the TSC voted to make the OVM the base for the UVM. So what Accellera will standardize is all of the current OVM augmented by good ideas from OVM World Contributions, VMM, and the collective experience of the TSC members.
Call it “the best of VMM and OVM” if you want, but I do think that the choice of the OVM as the base for the UVM is an important part of the story and worth noting.
Tom, yes OVM will be the basis for the UVM, with much-needed features from VMM – plus additional ideas – added into the new standard. I must say, after a rocky start in the VIP-TSC, it’s great to see Cadence on-board with UVM!
It’s nice to see that my dream of a universal verification methodology will be realized
Thanks to everyone who compromised to make this happen.