I can hardly believe it. I’ve been in the EDA business since 1980 when I joined TI’s Design Automation Department after graduating from Cal Poly with my BSEE. Since 1995, much of my attention has been focused on EDA standards. I reached a moment of truth this year when I admitted, albeit reluctantly, that I could be called a standards-lifer. So, I decided it’s time to share my perspectives on what’s going on in the standards arena. Welcome to my blog - I can’t wait to hear from you! Back to our regularly scheduled standards… VMM
Posted by Karen B on August 5th, 2009
The bagpipes have played at the 46th Design Automation Conference. Customers and vendors have gone home. The Moscone Center is being readied for the San Francisco International Summer Gift Fair and the Gourmet Housewares Show which start in 2 days. So it’s time for me to get back to the standards game.
I haven’t written anything about VMM since last October, but that doesn’t mean nothing has been happening with this standard verification methodology. VMM stands for “Verification Methodology Manual“, but it’s much more than a book. VMM comes with a standard library, applications, macros, utilities, and other supporting technologies – available to everyone at no cost. The latest advancements in beta now include TLM 2.0 support, block-to-top reuse, hierarchical phasing, and a lot more. The details are available at VMM Central. In addition, the VMM for Low Power was published early this year to help chip designers prevent or overcome challenges unique to low-power IC verification.
VMM is alive and well. With 500+ projects actively deploying VMM, 50+ user papers, and tens of millions of lines of user code, it is indeed thriving. Chip design companies are continuing to adopt and leverage VMM in their verification strategies. EDA tool vendors, IP providers, training companies, and service providers are continuing to join the VMM Catalyst program (more than 60 to date). And the VMM for Low Power is receiving rave reviews.
Peggy Aycinena of EDA Confidential wrote one such review. I particularly like her summary of Chapter 8: Rules & Guidelines – sixteen simple (well, not really) rules that are detailed in the methodology for highly effective verification of low-power chips.
There’s also good progress happening in the Verification IP standard committee of Accellera. The committee’s chair, Tom Alsop, published a good article in the current issue of Chip Design Magazine describing their accomplishments to date. My favorite part is the promise that once their recommended practice document is submitted to the Accellera board for approval this summer, the committee will begin work on their long term commitment to create a common base class library.
Since the publication of the original VMM in 2005, its adoption as an industry standard has shown how valuable it is to modern chip designers.
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