I can hardly believe it. I’ve been in the EDA business since 1980 when I joined TI’s Design Automation Department after graduating from Cal Poly with my BSEE. Since 1995, much of my attention has been focused on EDA standards. I reached a moment of truth this year when I admitted, albeit reluctantly, that I could be called a standards-lifer. So, I decided it’s time to share my perspectives on what’s going on in the standards arena. Welcome to my blog - I can’t wait to hear from you! What I'm going to see at DVCon, Feb 24-26 2009
Posted by Karen B on February 19th, 2009
DVCon, the Design and Verification Conference and Exhibition, will be held next week in San Jose CA at the Doubletree hotel. Now, more than ever, techniques and strategies for lower-cost, higher-quality-of-results IC development are imperative. In today’s <you-know-what> economy, the total cost of design has to be lowered, and that’s what many of the DVCon tutorials, sessions, and panels will address – either directly or indirectly.
The Accellera-sponsored conference again has a technical focus, aimed at IC design and verification engineers. Attendees will have a variety of topics to learn about. Here are some of the events I plan to attend:
Tuesday, Feb 24:
- All the tutorials (yes, I’ll be the annoying person who leaves early or comes in late).
- Accellera’s Update and Technical Excellence Award
- Exhibits
Wednesday, Feb 25:
- System Validation (Synopsys)
- Opening Session
- Verification Methodology
- Case Studies of OVM (Cadence)
- Keynote – Techonomics of Verification
- Not-Cooley Panel – EDA: Dead or Alive? (Alive, I say!)
- Exhibits
- SaaS Roundtable
Thursday, Feb 26:
- Verification Methodology
- Risky Business (Mentor)
- Low End Power Management
- Mixing Formal with Simulation
- Best Paper Award and Closing Session
Social media will play an interesting role in DVCon this year. There will be blogging and twittering – set your Twitter search for #dvcon. (I’m karenbartleson on Twitter if you want to follow me.)Â Plus, a rather interesting tool from Zerista has been set up for DVCon attendees. I’ve never used “social event software” like this before (unless you count Evite) so it will be interesting to see if it’s useful, fad-ish, or distracting.
Finally, I expect there will be a noteworthy announcement or two at DVCon. If you don’t hear news in the hallways of the DoubleTree, you’ll be sure to hear it through a variety of communications channels via Web 2.0. Might I remind everyone that we IC engineers and EDA developers built the internet? 
See you at DVCon!
EDA standards blog The Standards Game
DVCon Design and Verification Conference Accellera
VMM Verification Methodology Manual open verification methodology OVM
Unified Power Format UPF CPF IEEE standards IEEE P1801 low power standard
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Hey Karen,
Given the state of the economy, I am glad to see that the EDA industry is still moving forward. It will be interesting to see how tools like blogs and Twitter will be used to disperse information and help form new standards.
twitter.com/thenextwriter
Hi Karen, a month ago you wrote about Zerista: Plus, a rather interesting tool from Zerista has been set up for DVCon attendees. I’ve never used “social event software” like this before (unless you count Evite) so it will be interesting to see if it’s useful, fad-ish, or distracting.
Would you be available to discuss your experiences with the tools?
Brian Slawin
bslawin@busyevent.com
888.788.4896 x112