Archive for February, 2009

In the world of social media, pictures are a must. So, I bought a Flip camera and played around with it at DVCon. You’ll see I’m not much of a video or image producer, but maybe you’ll get a kick out of my attempts. Mercifully, I’ll only show a few…

Twitter is a fascinating social media tool, and several of us used it during DVCon. Rather than a  traditional narrative about what I saw and did at the conference, I thought it would be interesting to capture my tweets that I posted throughout the conference. Let me know if you love or hate it. You can find all the DVCon tweets various ways with a search.  (If you’re curious about Twitter, I’d enjoy sharing what I’ve learned about it.)

In looking over what I sent to the Twittersphere, I realized I was worried about the attendance at DVCon (lots of head-counting in the tweets) due to the economy. I was relieved to see the sessions fairly full and happy that the attendees seemed engaged and getting value from the conference. And I was delighted when some of the #DVCon Twitter followers who couldn’t attend the event said:

@karenbartleson, @jlgray, very impressive tweeting – I feel like I am at #dvcon!

Going to bed after a very long day at a client. Looking forward to DVCon updates tomorrow.

@jlgray @karenbartleson I need a 12sec vid so I can feel like I’m @ #dvcon I am sitting here with corny badge holder around my neck waiting

Thx for all the conference twittering. It’s almost as if I was there this week. No, not quite.

@jlgray, @karenbartleson, bravo! Nicely twittered. I enjoyed that – #dvcon

Now, here’s a stream-of-consciousness snapshot from karenbartleson via Twitter:

Day 1

I’ll say this once so i don’t repeat myself the next 3 days at #DVCon. All my tweets are my own humble opinions.

#dvcon tutorials on VMM and OVM have decent attendance – roughly 50-60 each. Encouraging.

Synopsys announced the VMM-LP at #DVCon. It’s our low-power verification methodology manual with ARM and Renesas. http://tinyurl.com/bhddgm

in Mentor’s #DVCon tutorial, Fitz is educating audience about UPF, the Unified Power Format for low power design.

papers at #DVCon are reviewed blindly and accepted for their technical merit.

at Accellera lunch at #DVCon, Shrenik asked the nice-sized audience if they are familiar with Accelllera. Almost all said yes!

Karen Pieper, Accellera’s technical committee chair, gave an update on Accellera’s standards. I found it impressive.

#DVCon Steve Bailey, chair of P1801 – UPF 2.0 is giving an overview. The working group worked hard.

#DVCon UCIS committee is reviewing donations from Synopsys and Mentor.

#DVCon Results of the Accellera OVL survey had >100 responses, >half users, 70% use ABV, SystemVerilog much more than others

#DVCon Sri Chandra wins Accellera technical achievement award for Verilog AMS. Congrats, Sri!

#DVCon is definitely the right venue for the annual Accellera member meeting.

If you’re waiting for me to talk about VMM vs. OVM at #dvcon, don’t hold your breath. Ain’t gonna do it. Wouldn’t be prudent.

approx. 45 people in Cadence’s OVM tutorial at #dvcon.

@newtechpress try searching for #dvcon. you’ll see individuals twittering.

I’m at the exhibits at #DVCon. There are a lot of people here.

Day 2

#dvcon bkfst. Ken McElvain talking about s/w content of SoCs. Looks like some attendees didn’t set their alarms. But good Q&A.

#dvcon Opening remarks by Tom Fitzpatrick, General Chair: 150 people at tutorials. >600 attendees year. Remarkable in this economy.

Twittering helps the social networking at #dvcon as well as the technical networking, per Fitz.

IEEE-SA being recognized at #dvcon opening remarks.

Ambar Sarkar, Technical Program Chair of #dvcon gave stats: 9 panels proposed, 117 abstracts submitted (8% increase), new sessions added.

eating Cadence lunch at #dvcon. another nice-sized audience. listening to OVM a few OVM case studies.

@dennisbrophy The new corporate dues model is a major step forward. Everyone attending #dvcon has an opportunity to benefit. Well done!

oops! The #dvcon speaker from Sirf just called CPF the Cadence Power Format.

the large audience at Aart de Geus’ keynote at #dvcon is engaged and enjoying his talk quite a bit.

#dvcon Aart says that 65nm ICs are half hardware, half software and software content is increasing. Guess what is in all of our futures?

#dvcon The next wave of IC design will be System Prototyping which is virtual prototyping + rapid prototyping + IP.

Shrenik Mehta, Accellera Chair, awarded Accellera’s Technical Excellence Award to Sri Chandra from Freescale for Verilog-AMS work. #dvcon

Karen Pieper, Accellera’s Technical Committee Chair, accepted the award for him. He was on the phone in India! #dvcon

Peggy Aycinena is now moderating the exec panel at #dvcon, formerly done by John Cooley for years.

#dvcon exec panel abstract and lineup are here http://www.dvcon.com/html/panel1.html

#dvcon Peggy asked "Is EDA press dead or alive?", said maybe they’re chars on a tweet or sponsored articles – not journalism, but oh well.

I think I’ll tell Peggy at #dvcon that bloggers & twitterers like @jlgray, @harrytheasicguy, & me are members of the "Civilian Press Corps"

#dvcon Ajay Bose, Atrenta: EDA is not dead because if it were, semiconductors would be dead and that’s not going to happen.

I now have the raw material for a short film from #dvcon "The Blair Witch EDA Panel".

I admit that I don’t have enough SIADD http://tinyurl.com/dymdgj to tweet and flip video simultaneously at #dvcon.

maybe solving system-level design and hw/sw design issues will ensure that EDA isn’t dead. #dvcon

oh dear, here come the commercials at the #dvcon exec panel. i hope the customers like them.

Regardless of the "official" survey results, I like it better than the past Cooley panels. My informal Twitter vote.

OMG. Are the old EDA people supposed to die now? The #dvcon panel is taking a depressing turn.

#dvcon peggy just asked what the eda companies are doing for universities. snps has a big program (it’s mine).

doing my own tools would mean no interoperability problems? i don’t agree. design data would still flow between tools w/buggy i/fs. #dvcon

yes, peggy, as an employee of an eda vendor, i am working as hard as i can for my customers. #dvcon

#dvcon for the 7 panelists, on your roadmap?: cad for biology 0; carbon nanotubes 0; cloud computing 3; multicore/threading 6

#dvcon gabe challenged the eda industry to think beyond semiconductor company probs they hand us today and solve their probs of the future.

#dvcon SaaS session, just now got connection/computer working (blackberry out of service all day). missed tweeting it, now Q&A going on.

#dvcon SaaS session: discussion on behavior changes and license model changes.

#dvcon I think Harry is recording the audio. Peggy is here. Richard Goering is here. Should get some good info from them post-event.

a well-known VHDL expert, @thenextwriter, published a thriller/adventure novel. can’t wait to read "Lost in the Sky" by Douglas Perry.

Day 3

just came from the #dvcon steering committee meeting. i will have a special role next year.

Eating Mentor’s risky business lunch at #dvcon. Fortunately, Steve Bailey is not in his underwear dancing to Bob Seger.

#dvcon session 11 low power mgmt. About 25 attendees. OVM/CPF VMM/UPF. Ah, the standards game. http://www.synopsysoc.org/thestandardsgame

#dvcon Gary Delp talking about 1801 aka UPF standard. I always like to hear him speak. He has 45 patents
! I’m not worthy.

#dvcon TI’s Freddy Brembaron is presenting a UPF example. Like Gary Delp from LSI, it’s great to hear real users talk about UPF (1801).

#dvcon panel on mixing formal verification and simulation. About 60-70 attendees.

#dvcon panel on mixing formal verification & simulation. ~75 attendees. Tools are easy to use, Methodology is hard.Audience very engaged.

#dvcon attendees voted. Best paper award & $1K went to 11.3 Low Power Verification Methodology using UPF. Texas Instruments & Mentor.

DVCon, the Design and Verification Conference and Exhibition, will be held next week in San Jose CA at the Doubletree hotel. Now, more than ever, techniques and strategies for lower-cost, higher-quality-of-results IC development are imperative. In today’s <you-know-what> economy, the total cost of design has to be lowered, and that’s what many of the DVCon tutorials, sessions, and panels will address – either directly or indirectly.

The Accellera-sponsored conference again has a technical focus, aimed at IC design and verification engineers. Attendees will have a variety of topics to learn about. Here are some of the events I plan to attend:

Tuesday, Feb 24:

• All the tutorials (yes, I’ll be the annoying person who leaves early or comes in late).
• Accellera’s Update and Technical Excellence Award
• Exhibits

Wednesday, Feb 25:

• System Validation (Synopsys)
• Opening Session
• Verification Methodology
• Case Studies of OVM (Cadence)
• Keynote – Techonomics of Verification
• Not-Cooley Panel – EDA: Dead or Alive? (Alive, I say!)
• Exhibits
• SaaS Roundtable

Thursday, Feb 26:

• Verification Methodology
• Risky Business (Mentor)
• Low End Power Management
• Mixing Formal with Simulation
• Best Paper Award and Closing Session

Social media will play an interesting role in DVCon this year. There will be blogging and twittering – set your Twitter search for #dvcon. (I’m karenbartleson on Twitter if you want to follow me.)  Plus, a rather interesting tool from Zerista has been set up for DVCon attendees. I’ve never used “social event software” like this before (unless you count Evite) so it will be interesting to see if it’s useful, fad-ish, or distracting.

Finally, I expect there will be a noteworthy announcement or two at DVCon. If you don’t hear news in the hallways of the DoubleTree, you’ll be sure to hear it through a variety of communications channels via Web 2.0. Might I remind everyone that we IC engineers and EDA developers built the internet?

See you at DVCon!

EDA standards blog The Standards Game
DVCon Design and Verification Conference Accellera
VMM Verification Methodology Manual open verification methodology OVM
Unified Power Format UPF CPF IEEE standards IEEE P1801 low power standard
ďż˝

In a few short weeks, the IEEE draft standard, formally known as P1801: Draft Standard for Design and Verification of Low Power Integrated Circuits, will complete its ballot cycle. Assuming the final steps go smoothly (and I have no reason to believe they won’t), our industry will have a new IEEE standard officially called 1801. The “P” and “Draft” will be removed as it receives final approval from the IEEE Standards Association.

Most of us know this standard as the Unified Power Format – UPF. Ratification by the IEEE-SA is a significant event, and the P1801 working group should be heartily congratulated. I think the best is yet to come, and I’ve saved it for the end of this article. (It’s fair to peek ahead.)

In early 2007, UPF became an official Accellera standard. A year later, Accellera transferred UPF to the IEEE, as it always does, where it obtained the moniker P1801. It is an entity-based standard, jointly sponsored by the IEEE-SA’s Corporate Advisory Group (CAG) and Design Automation Standards Committee (DASC).

Everyone following or participating in the standards game probably remembers the “standards war” associated with UPF and the alternative format, CPF. The outcome of which was phrased, “It’s better to have 2 standards than 20″.

As a multi-vendor backed standard, though, UPF had an advantage. Even two years ago, UPF had support from several vendors, not just one. A standard that doesn’t have broad vendor support isn’t really much of a standard. This video from DAC 2007 shows two of the EDA competitors who came together to create a common standard for low power design and verification.

 �

 

(It’s interesting for me to see this video again. Much has changed in two years – Richard Goering isn’t with EETimes and Yatin Trivedi isn’t with Magma. But some things never change – Dennis Brophy is still out in space.  Just kidding, Dennis! You know you’re my good friend for life.)

So, what do I think will happen after P1801 becomes 1801?

Adoption will continue to increase. Not only will more new and existing EDA tools support the standard, but more customers will use it in their advanced, low power IC designs.

A new project will begin for the next major version of 1801. I’ve seen some interesting proposals on how to expand 1801 to cover areas beyond design and verification. Starting a new project in the IEEE means 1801 will again become P1801.

And convergence with CPF will finally occur. This will be the best part of all. A common industry standard for low power design and verification will satisfy what customers have needed all along.

EDA standards blog The Standards Game
low power design low power standard upf unified power format
Unified Power Format UPF CPF Accellera IEEE standards IEEE P1801 low power standard

It’s time for the next Commandment for Effective Standards.

Number 5 is: Realize There Is No Neutral Party.

For anyone involved in the standards game, this knowledge is crucial. Everyone participating in standards has a mission to accomplish, be it for business, law, safety, technology, or personal reasons. No one would spend a valuable minute or a precious penny on a standards activity for which they didn’t care about a specific outcome.

People can be surprised when they come to understand how not-neutral standards participants are. An engineer who is new to a committee can be horrified to discover that another committee member has been purposely delaying progress by throwing up smokescreens that sound like policy discussions. An EDA vendor can be perplexed when another vendor who has participated in developing a standard for years suddenly announces an alleged essential patent. And a customer can be shocked upon discovering shenanigans that feel like vandalism when attempting to survey the industry about which of two standards is preferred.

I’ve always chuckled when an organization claims to be a “neutral third party”. It happens usually in the midst of a standards struggle, and on the surface it seems to be an answer to a settlement. In truth, the NTP (how’s that for a new acronym?) has something to gain. In the case of one famous – I should say infamous – standards battle (see the last paragraph of the article), the NTP stood to increase membership and bring in additional funding.

Keeping the 5th Commandment for Effective Standards in mind before jumping into a standards activity can help you gain a broader perspective and quell some of the emotions associated with any skirmishes that might erupt.

If anyone can find a truly neutral party in the standards game, I’d be fascinated to learn about it.

EDA standards blog The Standards Game
10 Commandments effective standards
power standards UPF Unified Power Format CPF Common Power Format
verification standards VMM Verification Methodology Manual OVM Open Verification Methodology
patents essential patents SystemVerilog P1800