Archive for 2009

On the last work day of the year, I thought I’d write a non-work, non-standards related post.

I really like Brussels sprouts.  Even as a child, I enjoyed the little cabbages, peeling the leaves off one at time to eat them slowly.  This year I discovered some wonderful produce stands in Half Moon Bay CA that sell Brussels sprouts still on the stalk.

If you’ve never seen how they grow, it’s pretty amazing. Here’s a picture. The stalk is about 4 feet tall, and the sprouts are smaller towards the bottom and quite large on the top. The sprouts are easily popped off the stalk and ready to cook in so many delicious ways.

Not only do I like to eat them, but I get a kick out of carrying a stalk of sprouts through the San Francisco airport. Carrying a stalk of Brussels sprouts makes an otherwise boring wait in the airport quite fun.

Talk about a conversation starter. People smile at them. “I love Brussels sprouts,” they say. “Here’s my favorite recipe,” they share. People are amazed by them. “I never knew how they grow,” they tell me. “Wow! That’s beautiful,” they exclaim. And sometimes, people even cringe. “What *are* those? Brussels sprouts? I hate them!”, they state. I always ask them if they’ve ever tried them, and it’s funny how often they say “no”.

The TSA agents enjoy the Brussels sprouts stalk, too. One of them asked me if it was a weapon. I told him of course not, it’s a vegetable. His partner said, “Ah. A third-grader’s worst nightmare – death by Brussels sprouts.”

My thanks to all of you who’ve read my blog in 2009, and thanks also for your comments here and to me as @karenbartleson on Twitter. If you have a Brussels sprouts story or recipe, do tell!

I wish you and your loved ones a wonderful holiday season and a successful 2010!

I’m nearing the end of my series, “The 10 Commandments for Effective Standards”. Here is the 9th installment. It looks at how the standardization process can be accelerated and how standards can have a better chance of being adopted by industry.

The 9th Commandment for Effective Standards is: Start With Donations, Not From Scratch.

In the fast-paced EDA industry, spending too many years producing a standard can cause the standard to be pretty much obsolete by the time it’s finished. A sure way to speed up the standards process is to start with donations of already-proven formats, technology, and methods. Creating a foundation for a standard with techniques that have been shown to be useful gives a working committee a big head start. It also means that bugs or limitations may have already been addressed, lightening the load for the committee.

It’s important for the working committee – and its parent organization –  to allow donations to come from more than one source. Limiting contributions to a single company can be met with skepticism. It can also make committee members suspicious that a single company’s agenda is being pushed or that the standardization process isn’t open.

Of course, if a single solution is so elegant and welcomed by the committee that it’s not interested in other donations, it’s fine to proceed. However, this sense should be widely accepted, and committee members shouldn’t be blocked from making donations if they wish to.

On the other hand, if only one donation is made and no other donations are forthcoming, it could indicate that there’s no real need for a standard. In this case, even if much time and effort are put into producing the standard, it could end up sitting on a shelf, unadopted.

Donations can be made in a variety of ways, and established standards-setting and standards-development organizations have policies governing them. At times, owners can contribute their solutions through licensing schemes, but it’s critical that the terms be reasonable and non-discriminatory. Also known as RAND terms, this insures that all interested parties will have access to the standard for use in their products and services.

I know that some industries have to create standards from scratch before products can be developed. Yet, in my industry I’ve found that donations of proven technology result in highly effective standards.

I like the new model for IEEE-SA corporate membership. I like it so much that I was one of the first to sign up, enrolling Synopsys for an advanced membership. As an advanced member, Synopsys employees can participate in an unlimited number of corporate (entity-based) standards projects without paying additional project fees. We’re saving money, our budgeting is simpler, and our engineers no longer have to justify the project fees to their managers.

Articles about the new model can be found on EETimes, Urgent Communications, and Gabe on EDA. The articles describe the model, explain why the change was made, and highlight the benefits of the entity-based standards process. What you won’t read about in these articles is the effort that went into developing, proposing, and obtaining approval for the new membership model.

When the IEEE Standards Association’s governing committees have a problem to solve or a project to undertake, they create task forces to do the work. Called “ad hoc committees”, the task forces are comprised of volunteers who serve on the governance committees and IEEE-SA staff members to support them. The ad hoc committees develop solutions or tackle projects, then seek recommendations and approvals from the higher authority governing committees.

One such ad hoc committee was formed when the IEEE-SA’s Corporate Advisory Group (CAG) recognized that the original corporate membership model might be a limiting factor in starting new entity-based standards projects. Chaired by Dennis Brophy, this ad hoc spent a couple of years creating and adjusting proposals that would meet the needs of corporate members as well as the IEEE-SA itself. The membership model had to be cost-effective, have distinct benefits, and be enticing for corporations and other entities. It also needed to be non-disruptive to the IEEE-SA’s policies and finances. Several iterations were required before the model satisfied the stakeholders. Dennis and his ad hoc’s members stayed persistent and encouraged throughout.

It’s good to see the fruits of the ad hoc committee’s labor. And even better to taste them.

This is the 8th installment in my series, “The 10 Commandments for Effective Standards”. If you’ve missed the previous entries, have no fear. There’s no god of standards to whom you’ll have to pay penance. And if you’re interested, the first 7 commandments are in the archives.

Commandment #8: Recognize there is more than one way to a standard

In the early days of the electronic design automation industry, EDA standards were primarily produced by the IEEE’s Design Automation Standards Committee (DASC) or by the Electronics Industry Association. These formal standards organizations sponsored the ratification of two of EDA’s most well-known standards, VHDL and EDIF, respectively.

Over time, however, the process of creating EDA standards became protracted and inefficient. As technology advancements sped up, EDA standards fell behind, and by the time they were ratified, they were practically obsolete. Lore had it that EDA standards took 3 – 6 years to complete. With new semiconductor technology nodes coming along every 3 years or so, standards were clearly not keeping pace.

When the collective EDA industry “we” realized this, new models for standardization were developed. Plus, the venerable IEEE introduced its corporate standards program, and some important EDA standards were produced in record time.

I’ve grouped the standardization models into 4 categories: closed proprietary, company open proprietary, formal committee, and open source. All of these are in play, with each having different strengths and weaknesses. Here are their characteristics and an example of each:

Closed Proprietary

Characteristics

• owned by a single company
• available only to that company’s customers
• fast to evolve and well-supported
• other vendors are not allowed to use them
• greatly reduces tool interoperability

Example

• Cadence’s Physical Design Kit format (PDK)

Company Open Proprietary

Characteristics

• ensures access to everyone
• immediate availability, timely releases
• well-established, well-maintained standards
• significant resources applied by owner

Example

• MAP-in (Milkyway Access Program)

Formal Committee

Characteristics

• consensus-based processes
• membership open to all
• members sincerely want standard to succeed
• can be slow or fast to evolve depending on process

Example

• Unified Power Format (UPF) / IEEE Std. 1801

Open Source

Characteristics

• open to everyone
• members want the standard to succeed
• single person, entity, or company manages enhancements from and to a community
• fast to adoption and fast to evolve
• “forking” can occur without management and commitment

Example

• Open SystemC

Which model is selected for an EDA standard to follow depends on several factors including: maturity of the technology, rate-of-change requirements, industry demands, and business climate. Each has its place in today’s standards game.

The keynote at the 22nd EDA Interoperability Forum was delivered by Subodh Bapat, Vice President, Energy Efficiency and Distinguished Engineer at Sun Microsystems. Titled “Groovy Green Computing: Battling the Mushrooming Use of Power”, his presentation was not simply interesting, it was relevant to what many of us talk about and work towards – sustainability.

Sustainability, a.k.a. green, is a topic of much visibility in the world today. With increasing global demand for more compute power comes increasing hunger for energy. Sun and countless other companies, organizations, and governments are finding ways to curb the appetite. Subodh’s keynote was full of thought-provoking information such as data center power consumption increases 10X every 12 years. (Hm. Sounds like a “More’s Law” to me.) Floor size of the data center increases accordingly, too. By 2012, worldwide data center power consumption costs could be as high as $250B, compared to $30B-40B a couple of years ago. An enormous data center – 750,000 sq. ft., needing 80MW of power – is being planned for Miami to route Latin American and Caribbean data traffic. And it will need a special power plant for itself! A power supply for a computer is only 60% efficient. (Here we semiconductor people are, lowering power consumption of chips and the savings are swamped by the power supply.) Cooling fans and other things also contribute to a computing system’s energy requirements. It’s important then, to analyze the entire system -  and data center – to minimize overall power use.

Energy consumption will come under more scrutiny and government regulation. Several advanced and not-so-advanced techniques are being deployed to meet data center goals of getting maximum work out for the amount of power consumed and ensuring minimum power usage when idle. Facilities and IT departments – typically the ones who deal with power consumption challenges – are beginning to work together for better solutions. Creative ideas are being tested. “Hot Aisle Containment” doesn’t let hot air generated by server racks mix with cool air coming in. Putting a data center underground in an abandoned coal mine allows the earth to absorb heat without energy required for air-conditioners (although this sounds dangerous for workers to me). Pumping hot air from a data center through underground “earth pipes” also uses earth for cooling. A hospital saves energy by using water warmed in their data center to do their laundry. A wastewater treatment facility needing warm water to maintain algae growth gets it from a nearby data center. And my favorite is “Air Side Economization”, which is a fancy term for opening the windows. Data centers in cool climates need not use energy for air-conditioning when it’s free with ASE.

Subodh described three aspects to be considered together for reducing data center power consumption: proportionality + totality + agility. Proportionality is balancing workload with power consumption. Totality is looking at every component, not just optimizing one. Agility is being responsive to fluctuations.

At the end of his keynote, he said that yes, we in the semiconductor industry are helping, too. Our low-power design and verification methodologies along with advanced semiconductor technologies are helping make a sustainable planet for us all. Thank goodness.

I think it’s fun to write blog posts during a conference. In addition to giving highlights from presentations, I try to capture interesting comments that speakers make which aren’t on their slides and human interest stories that happen during the event. Here’s my eye witness account from Synopsys’ 22nd EDA Interoperability Forum. (That’s me in the photo, making the opening remarks.)

We continued our playful theme of “Peace, Love and Interoperability” for the Forum.Titles of presentations included “Flower (Low) Power”, “Make (Verification) Plans, Not War”. and “Turn on! Tune in! Tape Out!”. Presentations will be available on our website after November 13, along with presentations from past Forums.

Several people wore tie-dyed shirts to the Forum and made jokes about how much hair we all had in the ‘60s. I saw some new faces and many dedicated interoperability practitioners who attend the Forum regularly. Synopsys purchased carbon offsets in a step towards a sustainable Earth. A gentleman from Jasper won a backpack full of prizes, and the lunch buffet was tasty and nutritious. There was a bit of action on Twitter as well – search the hashtags #EIF22, #snps and #EDA to see some of the tweets.

Subodh Bapat, VP of Energy Efficiency at Sun Microsystems, delivered quite an interesting keynote about data center power consumption. (It will be the topic of my next post as this one is getting too long.)

The first speaker was Rajesh Kumar from Synopsys who gave an update on the Liberty library modeling standard. One of the key benefits the Interoperability Forum provides is insights into standards like Liberty that give EDA suppliers a head-start in developing interoperable tools.

Neil Songcuan, also from Synopsys, talked about the HAPsTrak standard input/output  connector that’s mounted on the HAPS rapid-prototyping board. Essentially all SoCs use some kind of rapid prototyping, and the standard I/O connector makes rapid prototyping easily deployable, promotes reusable hardware for future projects, and minimizes risk. This is the first time that the Forum featured a standard that’s actual hardware.

Richard Paw represented the EDA Consortium’s OS Roadmap Committee. This group produces guidelines for operating system and hardware platforms that help unify EDA tool support around common platforms. (It drives customers crazy when the tools they purchase don’t support the same platforms.) The guidelines will be updated in September 2010. Added will be SLES 11 (SuSe Linux) and Windows 7. Dropped will be SLES 10. In 6 months, the committee will review Windows XP, Vista, and the upcoming RHEL 6 (RedHat Enterprise Linux).

Dave Graubart represented the EDA Consortium’s Anti-Piracy Committee. He said it’s hard to feel the love when you’re getting ripped off. The committee estimates that 1/3 of all EDA software use worldwide is pirated or overused beyond the license agreements. Not scientific data, but troubling nevertheless for the EDA industry. It’s easy to find the stolen binaries so most of the 1/3 estimate comes from this, not misuse/overuse which is harder to find. There are potential techniques to help prevent this piracy and the committee will continue its work to solve the problem.

Cary Chin from Synopsys presented the current state of the 1801 standard, which was approved as an IEEE standard in March 2009. I’ve written a lot about this standard, and I’m relieved to see evidence of convergence – or at least interoperability – with the Si2/Cadence CPF (Common Power Format).

Ed Lechner, also from Synopsys, gave an update on the IPL Alliance which began 2.5 years ago. Users are proving out the standard which is based on OpenAccess and provides the industry with a means to create and employ interoperable PDKs (physical design kits). An interesting discussion followed Ed’s presentation about whether IPL Alliance members would provide 180 or 130nm offerings. The IPL Alliance has focused thus far on 65nm and smaller technology, yet one audience member contended that the analog/mixed-signal world is still at 250 or 350nm. Customer members will be able to bring their larger geometry demands, if needed, to the IPL Alliance.

One of the most interesting sessions at the Forum was a live, international demo of an interoperable PDK in use. 10 tools from 5 vendors were run using a single, interoperable PDK and a single OpenAccess database – with no data translation! “Far out, man,” was the introduction from SpringSoft which kicked off the demo (pictured here).

Frank Schirrmeister of Synopsys described the System-Level Catalyst program which accelerates the adoption of system-level design and verification. Among other benefits, program members receive access to Synopsys’ system-level and rapid prototyping products for interoperability development. A hardware/software interface can have lots of bugs, so system-level design and verification is a necessary step in the development process. As Frank stated, in a system it’s the software that’s the differentiator. And so is the hardware (depending on your point of view).

Dr. Andrea Kroll from JEDA Technologies spoke about automating model verification. Model developers can spend 30-40% of their time in verification, then the consumer of the model can spend the same amount (or more) verifying the model before using it. The standard TLM 2.0 model interoperability (a set of API calls, modeling styles, and rules) comes to the rescue.

Bill Neifert, founder of Carbon Design Systems (system-level modeling & validation tools), talked about validating complex software on a new hardware design. He showed a “virtual system lifecycle” starting with model generation and ending with model deployment.

Grant Martin from Tensilica talked about their ESL methodology and ISS-Innovator integration. (I remember working on Accellera’s policies and procedures with Grant a few years ago. I’m guessing he likes working on ESL more than P&Ps.) In the future, TLM 2.0 should be standardized via the IEEE 1666 working group. Grant suggested some improvements that could be made to the standard, and said Tensilica is happy to help. That’s the spirit I admire.

Robert Freeman from Synopsys said, “It’s all groovy with VMM 1.2”. He explained that a methodology is essential for significantly reducing the time needed to complete verification while finding the challenging, “strange” bugs. (In the old days, we knew that verification was finished by looking at the calendar, not by looking at the coverage.) Since a few people in the audience weren’t familiar with VMM, it was good that Robert talked again about VMMCentral and its resources.

Mark Gogolewski of Denali emphasized the important of verification planning because verification is incredibly expensive and time-consuming. He gave a practical description of how to do planning with Denali’s tools and Synopsys’ VMM Planner.  An audience member asked how flexible is the VMM planner for different architectures. Mark answered that he doesn’t write code any more (nor do I, for that matter), but his customers and engineering teams say it’s extremely contemporary, so  he’s confident that it’s flexible. Another question for Mark was how well does the VMM planner calibrate coverage, i.e., how intelligent is it? He explained that it’s dependent on the coverage library you define, and it’s an advantage of VMM because companies offer verification IP now that can be dropped in quickly. Plus, the VMM planner does quite a capable job moving through the data.

John Goodenough from ARM talked about VMM for Low Power, focusing on aspects that make standards like VMM happen to the benefit of industry. As VMM has done, engagement across the industry is required, not just with 1 or 2 players. (I’d say that ARM’s ecosystem is witness to John’s wisdom.) He also mentioned that electronic devices today need to operate in the lowest power mode possible not only for battery life, but also to be green.

Ambar Sarkar of Paradigm Works said there’s a tremendous amount of code required to reach the registers in a chip for verification. Home grown solutions have issues. With the RAL application – part of  the VMM standard – these issues are mitigated. Paradigm Works will make their implementation available on SourceForge.

Doug Smith of Doulos give some source code and examples of the new features of VMM 1.2. (Thanks to Doulos for providing each Forum attendee with a free copy of their VMM Golden Reference Guide.) As part of the beta program for VMM, Doug learned first-hand about these features and providing his technical expertise to the Forum audience again demonstrated the value of the Forum to its attendees.

The 23rd EDA Interoperability Forum will be held in Fall 2010. We’ll work hard again to bring solid value to everyone in the standards game.

Two events are coming soon that you might be interested in. On November 3, 2009 at 10am Pacific Daylight Time, OpenSystems Media will sponsor a webcast about the use of Twitter in the embedded systems marketplace. Social media practitioners from ARM, Intel, and Synopsys (me) will share ideas on how we’re using Twitter as a B2B marketing tool. Registration is open and the webcast is free. It will also be recorded and posted after the event.

On November 5, 2009 at 9am PDT, Synopsys will host its 22nd (wow!) EDA Interoperability Forum. The theme is “Peace, Love and Interoperability” and the keynote speech will be about green computing. We’ll provide updates on several important initiatives including IPL (for interoperable PDKs – physical design kits), VMM (verification methodology), and system-level interoperable flows. Everyone is invited, particularly tool developers at EDA companies. Registration is open and the event is free. Continental breakfast and lunch are included.

I hope you’ll be able to join me at these events and that you’ll receive valuable information from them.

There’s a day dedicated to just about anything you can imagine. Today the United States celebrates “World Standards Day” which is actually on October 14. World Standards Day marks the birthday of ISO, which will be 63 years old, and this year the focus is on climate change. There’s a big party and awards ceremony in Washington, D.C. tonight, but it’s sold out so I guess I’ll stay home.

It’s appropriate that on World Standards Day, I’m writing a little book about standards. It will be full of short ideas (Twitter style – 140 characters or less) based on my experiences in the standards game over the past 14 years.

As I researched my old writings for the short ideas, I came across one of the first newsletters I wrote when I joined Synopsys. It included our vision for standards:

We proactively support standards that take our customers and us into the future of electronic design. These standards increase productivity and solve design problems while leaving plenty of room for innovation.

It’s good to know that, on World Standards Day, Synopsys’ vision hasn’t changed.

Happy World Standards Day, everyone!

I know it sounds funny, but I’d been anxiously awaiting a press release. A new standard had been ratified by Accellera, the premier standards-setting organization in my industry of chip design automation. So as not to steal their show, I had to wait until their press release came out to share the good news.

Accellera’s working group, the Verification IP Technical Subcommittee (VIP-TSC), has completed the first of 2 milestones it set out to accomplish. The working group began about a year and a half ago, and I was optimistic that they would do a good job. They decided to divide the task of producing a verification standard into 2 parts, a “short term” and a “long term”.

Their “short term” standard is now complete and is called “Best Practices Interoperability Guide”. This document provides information about using SystemVerilog verification components in an interoperable testbench environment, and it includes a reference library. It supports both the Verification Methodology Manual (VMM) and the Open Verification Methodology (OVM) which should make everyone happy in the standards game.

Now it’s time for the group to start working on their “long term” standard. Their efforts will produce a common base class library that can be used in simulators from multiple design automation tool vendors. The common base class library will foster a broad (universal) verification methodology to benefit verification engineers and developers of verification IP.

Again I’m optimistic that the VIP-TSC will provide the industry with an effective verification standard. Hmm. Maybe they will call it the Universal Verification Methodology (UVM).

I’m looking back at the progression of the Open Compression Interface standard (OCI), now that it has been officially ratified by the IEEE as IEEE-Std 1450.6.1, “Standard for Describing On-Chip Scan Compression”. I wrote about OCI entering the balloting phase of IEEE standardization a little over a year ago. This standard allows design automation tools used for creating chip test programs to interoperate.

Chip testing is a complex, expensive undertaking with enormous numbers of test patterns required to check a chip’s functionality and performance. Electronic design automation tools are used to generate the massive amounts of patterns because the task is virtually impossible without automation. To handle the test patterns more efficiently, a technique called “on-chip scan compression” was developed by test engineers, using part of the chip itself. New EDA tools were created that supported the new technique. Yet, tool vendors used different means for passing data between their own tools. (Sound familiar?)

In the summer of 2005, the board of Accellera was asked to approve a working group that would come up with a standard for describing on-chip test data compression structures. If test tools used this interface standard instead of their own methods for passing data, customers would have greater freedom of choice among tools.

True of any standards effort, there were concerns. Would the algorithms inside the tools be standardized, effectively making the tools unsellable? Would one tool vendor’s format be forced down the throats of the rest? Would any key players refuse to participate in the working group? (Fortunately, it turned out that the answer was “no” to all.)

As I attended an Accellera board meeting that summer, I had to decide on behalf of Synopsys whether to vote “yes”  or “no” on the formation of the working group. With serious concerns still being aired, I had quite a deliberation happening in my head. The board took a break before the vote, and I was surprised how easy my decision became. Every member of the board who represented a company that was a customer of mine either took me aside to talk or whispered to me in passing. They all said, “You had better approve the working group. We really need this standard.”

Now that the OCI standard has completed its full approval process through Accellera and the IEEE, it feels good to know that when the customers said, “Do it!”, I did.