Archive for October, 2008

I don’t know about you, but I’ll be glad when the 2008 U.S. elections are over.  I mailed in my ballot this week and am now immune from those working hard to sway my vote.  I am honored and grateful to live in America, and I hope for a healthy, reunified country with global consciousness in 2009.

In The Standards Game, there is another important ballot underway: IEEE P1801, formally known as the “Standard for Design and Verification of Low Power Integrated Circuits”.  You may know this standard as UPF, the Unified Power Format, which was approved as an Accellera standard in February, 2007.  I’ve written about this standard in previous posts, describing its technical advantages and openness, plus the desire for a single industry standard.

The reason for UPF’s long official name in the IEEE is to distinguish it from other standards with the word “power” in their title.  As I might have mentioned, I’m a member of a couple of committees in the IEEE that approve standards in a wide range of electrical and electronic engineering fields.  I fondly remember one of my fellow committee members telling me that “low power” to him meant anything below 25,000 volts.  We certainly wouldn’t want a nuclear power plant generating the kind of low power that we think of in the semiconductor industry.

Low power IC design continues to be an imperative to support modern electronic product requirements.  The UPF/IEEE P1801 standard provides an open foundation for low power design solutions.  Leading suppliers of these solutions have built and are building tools and flows around UPF. 

UPF 1.0 from Accellera has been in real-world use, which has given users and EDA tool developers insights into ways to polish and enhance it within the IEEE P1801 Working Group. Oversights, ambiguities, verbosity, and backward compatibility have been addressed.  Enhancements have been made which include customer requirements that are new and some that were previously held for the next version.  Advanced power management solutions have been devised, and user interface improvements have been implemented.  

The resulting draft standard is now ready to receive the stamp of approval from the IEEE Standards Association.  Once it’s through the process, the “P” (which stands for “project”) will be dropped from UPF’s moniker and it will be simply, IEEE Standard 1801.

Finally, some very good news from the Si2 Low Power Coalition (the owner of CPF’s evolution) was delivered to the P1801 Working Group: the CPF 2.1 roadmap includes noteworthy efforts towards interoperability with P1801.  CPF, I’m sure you know, is an alternate format for describing low power design intent.

Congratulations to the IEEE P1801 Working Group as your draft standard goes through its balloting.  Everyone will be a winner in this particular election.

EDA standards blog The Standards Game
Unified Power Format UPF CPF Accellera IEEE standards IEEE P1801 low power standard

I read an article today titled “OVM vs. VMM: What’s Next?”  Overall, the article describes the emergence and current state of these verification methodologies, and it talks about a “battleground” – a word that is sure to excite readers.  In the world of the standards game, I don’t expect articles to always be 100% perfect, and I’m certain the author wrote his unbiased view, yet I noticed some inaccuracies and misconceptions that I’d like to comment on. 

• VMM from ARM and Synopsys was introduced in 2005, not 2007.  Two additional years of use in our fast-paced industry brings significant experience and maturity to a methodology.

• Mentor and Cadence did not “throw their technology into the open source world with Accellera”.  It was Synopsys that donated to Accellera our complete VMM implementation. Mentor and Cadence were vocally opposed to the verification methodology standardization work in Accellera.  Their open source introduction of OVM was separate from Accellera.  Fortunately, they are now active participants in Accellera’s verification IP technical subcommittee.

• Synopsys has not “kept the applications that run on top of VMM in-house”.  On the contrary, these are included in Synopsys’ VMM open source offering. 

• VMM is not proprietary.  It is freely available to everyone for download, without registration requirements – unlike OVM, I should add – at VMM Central.

I know that users want a single verification methodology standard, developed by a well-respected organization like Accellera.  Let’s bring VMM and OVM base class libraries together under a single, Accellera-sanctioned standard and enable EDA vendors to compete on superior methodology applications and automation.

 

EDA standards blog The Standards Game
VMM Verification Methodology Manual open verification methodology OVM
Accellera VIP TSC

For many years, OpenAccess had promised to bring interoperability to the industry via a common standard database.  Albeit fraught with challenges as it evolved, it has ultimately enabled a leading EDA provider (my company, Synopsys) to make a significant entrance into the custom/analog/mixed-signal IC design market. (Our solution is called Galaxy Custom Designer and is built natively on the OpenAccess database.)

Products aside, this is a success story in the standards game.  Until now, custom/analog designers were largely trapped into a single vendor solution because of long-time investments in legacy intellectual property (IP) which was written in a closed, proprietary language. This IP – the pcells (parameterized cells) that are in essence building blocks of an analog design – was developed and maintained over generations of technologies and engineers.  

Because the pcell language, SKILL, was – and still is – proprietary, only the owner of the language and the pcell developers were allowed to use it.  The owner of the language capitalized on its closed, proprietary nature, selling tools that interacted with the pcells to create custom designs and capturing a dominant market share.  Any other vendor who wanted to sell products into this market would have had to create a new language and get potential customers to rewrite their pcells in the new language.  The perceived ROI for customers was, obviously, negligible.  Duplication of effort, additional learning curves, interoperability faults between languages, and increased maintenance meant even the slickest new tools would have been too costly to obtain. The challenge went beyond simply to develop a new language for everyone to start using.  The enormous amount of legacy pcells had to come along without the requirement to be recreated from scratch.  Thus, designers were stuck with one vendor’s products and healthy competition was essentially non-existent in the analog market.

A common database for custom design which contained the pcells and provided access to them without using the proprietary SKILL would solve the problem.  OpenAccess has done just that.  After much wailing and gnashing of teeth in the standards arena, the previously closed, proprietary pcell format can now be accessed through the OpenAccess database.  Vendors can offer custom/analog/mixed-signal design tools that interoperate with pcells and each other.

The success story of OpenAccess is a good example of the 1st Commandment for Effective Standards: Cooperate on formats, compete on tools.

I have to admit that due to some kind of hard-wiring in my brain, every time I start typing “Custom Designer”, it comes out “Customer Designer”.  Now, *that* would be quite a product!

EDA standards blog The Standards Game
OpenAccess pcells IPL pdk
custom design analog design mixed-signal design

Hello, everyone interested in EDA interoperability and fans of The Standards Game.  I’d like to invite you to join me at the 21st Synopsys EDA Interoperability Forum, sponsored by Sun Microsystems.  I’m proud to say that I helped create this forum 10 years ago, and it has matured into a unique and valuable event.

Here are the details:

Thursday, November 6, 2008
9:30 am – 4:00 pm
Sun Conference Center, Santa Clara, CA at Agnews Historic Park

Register here to ensure your space.  There’s no cost to attend.

(Breakfast & lunch included.)

Agenda:

9:30am Registration & Breakfast  

10:00am – 11:30am  Interoperability for Custom Design

How to integrate EDA tools with Synopsys’ Custom Designer via its open environment

IPL Alliance’s standards for interoperable PDKs

Topics include:
- Liberty
- OCSI TLM-2.0
- VMM

Learn more about the Synopsys EDA Interoperability Forums and see previous presentations here.

I hope to see you all there. 

EDA standards blog The Standards Game