I can hardly believe it. I’ve been in the EDA business since 1980 when I joined TI’s Design Automation Department after graduating from Cal Poly with my BSEE. Since 1995, much of my attention has been focused on EDA standards. I reached a moment of truth this year when I admitted, albeit reluctantly, that I could be called a standards-lifer. So, I decided it’s time to share my perspectives on what’s going on in the standards arena. Welcome to my blog - I can’t wait to hear from you! Verification Standards Working Group is Launching!
Posted by Karen B on April 24th, 2008
I’m very excited today because the Accellera standards organization has chosen to form a technical subcommittee to define a standard for verification interoperability. I congratulate them on this decision. Verification engineers have been demanding a SystemVerilog-based verification standard for a while, and Accellera has taken an important step towards meeting the needs of the user community.
Users have asked for a standard methodology foundation for SystemVerilog to ensure maximum interoperability among verification components and easier collaboration between extended system-on-chip (SoC) verification teams.  A single Accellera-based standard can ultimately lower the cost of verification across the industry by propagating best practices, reducing re-implementation costs, speeding the creation of interoperable verification components, and improving overall verification productivity. Â
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Several of you (my customers) have already asked how to join and participate in the committee. Until a more formal structure is in place, feel free to send me an email (karenb @ synopsys . com) and I will pass on your request to the committee chair.Â
As I’ve stated previously, my company is ready to donate our VMM technology towards the standardization effort. When the Accellera committee solicits technology donations, we will immediately contribute ours. Synopsys’ VMM is defined in the Verification Methodology Manual for SystemVerilog book published in 2005, and it has been used in hundreds of successful projects and described in dozens of user-authored technical papers. Contributing VMM to Accellera demonstrates our support for customers’ need for a standard way of using SystemVerilog verification components.
There are other languages in use for verification, so the work of the Accellera committee could even provide the groundwork for possible interoperability solutions beyond SystemVerilog. With this effort underway, there can be momentum towards industry coalescence around common verification standards.
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Accellera VMM OVM verification standards open standards
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Bravo!
I think this is the right attitude:
Rolling OVM and VMM into a broader standard “is not rocket science,” she said. “I believe the two could come together.”
Karen as quoted by Richard Goering in SCDsource
Concerning the upcoming donation of VMM: “The most recent donation of VMM by Synopsys is most welcomed, it will encourage more users to utilize SystemVerilog in their verification flow, resulting in faster design releases and higher quality products.” commented Dr. Stanley Hyduke, chief executive officer of Aldec, Inc.
“The donation of VMM to the Accellera Standards Organization is a bold move on the part of Synopsys and should be applauded by the functional verification community at large. This kind of move is what encourages innovation and furthers the goal of reliability and predictability that Synopsys stands for.”, says Bruce Bergenfeld, CTO, Synterix Technology, Electronic Design Services.
“Synopsys’s VMM donation to Accellera provides increased benefit to the growing SystemVerilog ecosystem,” said Jeremy Ralph, CEO, PDTi.