Archive for April, 2008

I’m very excited today because the Accellera standards organization has chosen to form a technical subcommittee to define a standard for verification interoperability.  I congratulate them on this decision. Verification engineers have been demanding a SystemVerilog-based verification standard for a while, and Accellera has taken an important step towards meeting the needs of the user community.

Users have asked for a standard methodology foundation for SystemVerilog to ensure maximum interoperability among verification components and easier collaboration between extended system-on-chip (SoC) verification teams.  A single Accellera-based standard can ultimately lower the cost of verification across the industry by propagating best practices, reducing re-implementation costs, speeding the creation of interoperable verification components, and improving overall verification productivity.  

Several of you (my customers) have already asked how to join and participate in the committee.  Until a more formal structure is in place, feel free to send me an email (karenb  @  synopsys  .  com) and I will pass on your request to the committee chair. 

As I’ve stated previously, my company is ready to donate our VMM technology towards the standardization effort.  When the Accellera committee solicits technology donations, we will immediately contribute ours.  Synopsys’ VMM is defined in the Verification Methodology Manual for SystemVerilog book published in 2005, and it has been used in hundreds of successful projects and described in dozens of user-authored technical papers.  Contributing VMM to Accellera demonstrates our support for customers’ need for a standard way of using SystemVerilog verification components.

There are other languages in use for verification, so the work of the Accellera committee could even provide the groundwork for possible interoperability solutions beyond SystemVerilog.  With this effort underway, there can be momentum towards industry coalescence around common verification standards.

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The IEEE P1801 working group is making its way toward the final steps in IEEE ratification of the standard: balloting.  Now is the time for companies and organizations to join the group of balloters.  The deadline for signing up to ballot is Thursday, May 1, 2008, 11:59 PM Eastern Time.

To join the ballot group, contact Penny Stanton, IEEE-SA Balloting Center Administrator, at: sa-ballot @ ieee . org. 

P1801 will be an entity-based ballot which means “one company – one vote”.  This process offers freedom from blatant vote-stacking and promotes industry-relevant standards.  If your company or organization is already a corporate member of the IEEE Standards Association, you can join the ballot group and ballot without paying a balloting fee.  If your company or organization does not want to join the IEEE-SA, you can still join the ballot group and ballot by paying a per-ballot fee. 

You can check to see if your company or organization is a corporate member or find out who is your corporate member representative by contacting Patti Sulzer (p . sulzer @ ieee . org).  An IEEE-SA Corporate Member list is also available at: http://standards.ieee.org/sa-mem/corpmemlist.html

If your organization is not an IEEE-SA Corporate Member, but wishes to participate in this ballot, follow these instructions to become a member: http://standards.ieee.org/sa-mem/join.html#corporate

If your organization prefers to pay the per-ballot fee, please contact Penny Stanton, IEEE-SA Balloting Center Administrator, at: sa-ballot @ ieee . org.

The P1801 standard is descriptively named “Standard for Design and Verification of Low Power
Integrated Circuits”, and it is also affectionately known as UPF 2.0.  UPF, I’m sure you recall, is the Unifed Power Format standard from Accellera which is enjoying broad vendor and user support. 

The IEEE summary description of the P1801 standard is:

This standard establishes a format used to define the low power design intent for electronic systems and electronic intellectual property. The format provides the ability to specify the supply network, switches, isolation, retention and other aspects relevant to power management of an electronic system. The standard defines the relationship between the low power design specification and the logic design specification captured via other formats (e.g., standard hardware description languages). The standard provides portability of low power design specifications that can be used with a variety of commercial products throughout an electronic system design, analysis, verification and implementation flow.

Once P1801 completes the balloting process and gains approval from IEEE-SA governance, the “P” will be dropped and it will become the official IEEE 1801 standard for low power design and verification of today’s complex low-power ICs.

EDA standards blog
Unified Power Format UPF CPF Accellera IEEE standards IEEE P1801 low power standard

Hello, Everyone!  I had been wondering why none of my posts had received any ratings since the end of last year.  One of my subscribers recently pointed out that nothing was happening upon mousing-over (is that a word?) the stars.  I did a little investigation and found that an option had been incorrectly set which pretty much disabled the rating system for my blog.

 The system is now fixed, and I’m looking forward to more ratings from my friends at Cadence. 

The 2008 Synopsys Users Group (SNUG) in San Jose, California was truly a record-setting event.  Over 2,000 customers from more than 250 companies gathered in Silicon Valley to learn and share their experiences in the challenging world of modern IC design.  Highlights from SNUG include recognition and congratulations to this year’s award-winners.  Proceedings – papers, presentations, and tutorials – are now available for download from the Synopsys website.

For me, SNUG 2008 was especially rewarding because the “Meet the Bloggers” booth gave me the opportunity to meet many talented engineers, discuss standards topics of interest, and welcome new readers to my blog.  The booth was busy all evening, and my fellow bloggers and I got a kick out of distributing our “MOO MiniCards” – a clever alternative to old-fashioned business cards.  (If you would like MOO MiniCards from Synopsys bloggers, let us know!)

Here I am at the SNUG “Meet the Bloggers” booth, meeting customers, winning a challenge (ask me for details), and passing out MOO MiniCards.

photos courtesy of Ron Ploof, Synopsys’ New Media Evangelist

It’s no surprise that the most popular topic customers talked with me about is their interest in a verification methodology standard. They are anxious for Accellera to start a working group so they can participate in the efforts to solve a real industry problem. As I’ve stated before, Synopsys is supportive of this effort, and we are ready to contribute.

Customers also asked me about Synopsys blogs, specifically if they can comment back and ask questions on our blogs. The answer is absolutely “Yes”! If you have any feedback or questions for me or any of Synopsys’ bloggers, please don’t be shy. Ask and comment away! There is real value in open blog dialog – it’s the essence of contemporary communication.

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