Archive for 2008

As the year draws to a close, I want to wish all of you the very best during the holiday season. Let’s hope for a bright 2009.

Take care, everyone -
Karen

Standards and patents are a flammable combination, IMHO.  Let me give you the latest example from my realm.  SystemVerilog, aka IEEE 1800, is an EDA industry standard language for hardware description and verification.  The IEEE P1800 working group is finishing up the next version of the standard, hoping to begin the balloting process in the next couple of months. 

Recently, one of the entity (corporate) members of the P1800 working group made an interesting announcement.  Mentor Graphics said they hold patent claims that are essential for implementing the upcoming version of SystemVerilog.  Even more interesting is that they said they will *not* license these patents. 

If both of these statements are true – and I do not know if they are – the implication is that anyone who implements the upcoming version of SystemVerilog is open to patent infringement claims by Mentor Graphics. 

You can imagine that the P1800 working group participants are contemplating what to do next.  There are many questions coming and decisions to be made.  2009 is sure to start off with intrigue in The Standards Game.  I wish all of my readers a wonderful holiday season.

EDA standards blog The Standards Game
SystemVerilog IEEE 1800 P1800
patents standards essential patents

I’m intrigued by the latest step forward by the IEEE Standards Association: they are jumping into the pool – the patent pool, that is.  Through a collaborative effort with Via Licensing Corporation, the IEEE-SA will cultivate patent cross-licensing.  The goal is to increase adoption of IEEE standards, and technologies that employ the standards, by reducing legal hurdles imposed by patents. 

The concept of a patent pool is two or more companies agree to cross-license their patents that are related to a specific technology.  According to Wikipedia, one of the first patent pools was formed in 1856 which promoted mass production of sewing machines.  Related to a standard, a patent pool is formed of “essential patents” which are those patents that would have to be infringed upon in order to implement the standard. 

While a patent pool doesn’t solve every standard-patent issue, it can mitigate situations where companies desire to retain their patent rights while developing industry standards.  With a patent pool in place for a standard, streamlined processes expedite fair licensing, IP rights are preserved for patent holders, consumers of the standard have reduced risk of lawsuits, and legal barriers to adoption of the standard are significantly lower.

All this assumes that the patent holder is willing to license its patent, of course.  If not, I believe the patent holder should follow the 2nd Commandment for Effective Standards: Do Not Mix Patents and Standards.  There are at least a couple of ongoing legal battles over participation in standards committees by patent holders that lead me to say this.  They are the famous (or infamous) Broadcom/Qualcomm (with both sides claiming victory earlier this month) and Rambus (which could end up in the Supreme Court of the United States), both of which bring to question whether a patent holder can retain its IP rights while participating in the development of a standard which cannot be implemented without necessarily infringing on its patent.  Had patent pools been created in these two cases, perhaps the question would have been answered affirmatively.

EDA standards blog The Standards Game
IEEE IEEE-SA IEEE standards
patents standards essential patents

Hello to my readers while I’m participating in the IEEE Standards Association meeting series in Florida (not a hardship since the weather is beautiful here and it’s snowing in Colorado).  In conjunction with the meetings, the IEEE-SA held its annual awards ceremony which was an enjoyable and festive event.  The IEEE-SA bestowed several prestigious awards to individuals and a corporation that have made significant contributions towards standards in the electrical and electronic engineering realm.  This year, the recipient of the corporate award was…

… Mentor Graphics.  (Did you think I was going to say something different?)

The IEEE-SA corporate award is given each year to an entity member of the IEEE-SA for leadership and contributions that promote the IEEE-SA’s mission.  Past recipients are Intel, Motorola, HP, Sony, Lucent – Bell Labs, and IBM.  This year’s citation recognizes Mentor’s “visionary leadership in bringing greater efficiency to the standards development process in the Design Automation Standards Committee [DASC] through the adoption and support of the entity based development model”. 

I’m glad to write about this well-deserved award for Mentor, which I feel was given largely due to the efforts of my counterpart at Mentor.  (If you don’t know who he is and would like me to reveal his identity, just let me know and I’ll ask his permission.  He’s not shy, so I think he’d be amenable.)  His efforts towards reconstructing the DASC and promoting the IEEE-SA corporate standards program are noteworthy. 

In the spirit of industry cooperation towards continuous improvement of EDA standards, I send my congratulations to Mentor Graphics.

EDA standards blog The Standards Game
IEEE IEEE-SA IEEE standards

Accellera, which creates many of the standards in the EDA industry, wants your input on how to improve its Open Verification Library (OVL) standard.

Because functional verification takes the majority of time in the IC design process, new techniques are in demand and in use for reducing this effort.  For instance, an assertion-based verification (ABV) methodology can provide a sizable time savings in the debugging process and improve the quality of IC design verification.  Accellera’s OVL standard is a library of assertion checkers that can be used in simulation, emulation, and formal verification to support an ABV methodology.

The OVL technical subcommittee of Accellera is conducting a survey to learn about potential enhancements users would like and to measure usage of its assertion checkers. 

If you use OVL or an ABV methodology – and even if you don’t – the OVL subcommittee would like to hear from you.  Their survey is open now on their website.

EDA standards blog The Standards Game
Accellera OVL assertion-based verification ABV assertion checkers

Today’s economic climate is challenging to everyone, needless to say. Purchase decisions are scrutinized and budgets are tight for customers and suppliers alike. Now, as always, customers want choices and complete solutions. Interoperability – and suppliers’ programs that promote it – are now as important to customers as ever.

My company continues to be a long-time champion for interoperability. Please indulge me while I brag a little. Recently, a respected industry analyst said that “Synopsys is the king of interoperability” (scroll down to the “S” catagory). I admit that I felt a bit of a glow when I read this.

At Synopsys, we continue to work hard and spend significant resources to provide interoperable products and solutions to our customers. Our flagship interoperability program, in-Sync, allows scores of EDA companies to develop and test interfaces to our key products. Our catalyst programs help institute new and advanced industry standards such as SystemVerilog. Our standards program proactively provides the industry with technology and resources to help bring about much-needed standards via formal committees and open source. Presently, we are members of more than 30 standards organizations, our employees participate in 60+ standards-setting committees, and our products support as many industry standards. And for the most sensitive interoperability challenges (legal situations, for instance), our S.U.R.F. program provides secure facilities for other companies to debug problems with interfaces to our tools.

Why do we keep investing in interoperability programs?  Simple. Our customers require it. While we would certainly enjoy being the sole supplier of EDA solutions on the planet, we recognize the realities of healthy businesses. Working with competitors to allow our customers to make their best choices brings a certain measure of health to our company.

Something I learned very early in my career is that an IC designer’s job is *not* to run CAD tools.  It’s to produce a circuit design. This requires many tools combined in specialized flows, which of course implies interoperability.  Interoperability doesn’t happen by itself, and I’m proud to be part of a company that understands and cares about it. I believe our customers appreciate it.

EDA standards blog The Standards Game
open open standards in-Sync TAP-in SURF Synopsys interoperability EDA standards EDA interoperability

Thanks to Sean Murphy and Ed Lee for orchestrating an interesting and enjoyable bloggers’ Birds-of-a-Feather session at ICCAD.  There were almost 30 people in attendance, and we had some lively discussion. 

For those who missed my “lightening talk”, here is a summary.  I’d like to add pictures of my slides like John Busco did, but WordPress is causing me grief today.  Sorry this will be text-only until I can coax WP into cooperating with me.

I began by introducing myself with a picture of a traditional resume.  I’ve been in the industry for a long time, spending much of my attention in standards.  Over the past year, I’ve become a fan of new social media.  Hence, I’m Linked In, on Facebook, and on MySpace.  I started a blog on blogher.com where I can write about technology and express my opinions, independent from my affiliation with Synopsys.  For the BoF, however, I put on my hat as a corporate blogger from Synopsys and the author of this blog, The Standards Game.  If you believe the data, I have over 1,100 RSS subscribers.  I don’t know who most of you are, but I do know one of you: my counterpart at one of my competitors.  You told me that you always read my posts because every time I create one, it causes you trouble. 

Next, I described why I blog.  First, it’s fast.  I can provide information almost immediately.  I showed an example of posting my recent election as an Accellera officer on the day it happened.  The traditional press release announcement followed about 6 weeks later.  Second, it’s effective.  My responsibility in the standards arena is to help develop and promote the standards that greatly impact my customers.  I showed an example of how one of my posts resulted in customers learning about and joining an industry standards effort.  In the past, building an interested standards community was hit-or-miss, relying mostly on press releases and word-of-mouth.  Third, blogging is fun.  I have a post in progress called “Brussels Sprouts: Food or Weapon”.  Watch for it in the next few weeks.

Then, I talked about how I blog. To begin with, I commit to my calendar.  I have time blocked out every Thursday to dedicate to writing my post of the week.  (OK, I can’t wait to see who the first person will be to comment that I missed my post last week!)  It takes a bit of discipline to write regularly, but that’s what keep a blog alive.  I come up with ideas for posts by paying attention to what’s going on around me.  For example, I received an email notice about an upcoming ballot for P1801 (the IEEE standards project also known as UPF).  It was at the time of the U.S. presidential election, so I thought it apropos to write about another vote.  I don’t compose my posts in WordPress because it isn’t as feature-rich as Word.  But, I don’t use Word for its spell checker as evidenced by the famous “Owed to a Spell Checker” poem.  (Ask me if you haven’t seen it; it’s terrific.) I cut and paste into WP, read my post one more time, close my eyes, and push “Publish”.  Yes it’s true, I do not have any reviewers or approvers.

Finally, my new media mentor taught me that my blog is like a garden.  I tend it regularly, feeding it posts, watching ratings and comments, and weeding out spam.  (Actually, Askimet is great at filtering spam, but it occasionally traps a valid comment or lets something gross slip by.)

It is an honor to be part of the growing blogger community in EDA.  Thanks to all of you, my readers and supporters.

I’m attending the 21st Interoperability Forum in Santa Clara CA today.  We are continuing our 10-year tradition of providing technical and market-relevant information about interoperability to EDA tool developers.  As always, about a week after the event, materials from the Forum will be posted on our website. Rich Goldman, VP of Corporate Marketing and Strategic Alliances at Synopsys, welcomed the audience and kicked off the event as Master of Ceremonies. 

The first session in today’s Forum addressed interoperability for custom/analog design.  Scott Chase, our principal engineer of Custom Designer (Synopsys’ newly-announced product entry into the custom/analog market), gave a technical view into the product and its open environment.  Karim Khalfan, technical marketing engineer at ClioSoft, described their integration with Custom Designer via OpenAccess.  Ed Lechner, admittedly a marketing guy at Synopsys, gave a brief (yes, even as a marketing guy) overview of the IPL Alliance for interoperable physical design kits and pcells.  Neel Gopalan, chair of the IPL Alliance working group on properties and parameters, described the latest technology contribution made to his group.

During the general session, Rich provided a update on several standards and interoperability activities.  He then made a few moving statements about his pride in America after our election and the tough economic times that some of our friends are experiencing.

The next session focused on Open SystemC, with Frank Schirrmeister of Synopsys (and a fellow blogger) giving details on SystemC TLM-2.0.

The keynote speaker was the ever-popular EDA journalist Mike Santarini.  His engaging talk was titled, “EDA is an Ecosystem: Interoperability and the Future of EDA”, and he said the subtitle was “Tough Love” since our industry is facing challenges (as many industries are).  Mike reminded us that we are a really cool industry and must collaborate for success.

The next session dove into the details of VMM usage, with technical information provided by Mehdi Mohtashemi of Synopsys and Dr. Ning Guo of Paradigm Works.  Mehdi gave practical usage guidelines for VMM applications, and Dr. Guo described how to generate VMM-compliant environments.

The final session was dedicated to Liberty as applied to various (all) design flows.  Rajesh Kumar from Synopsys gave an in-depth update on new features in the library format, and the audience was able to ask detailed questions about syntax and usage.

As always, there were prizes, valuable Q&As, and good hallway discussions that could only be experienced by attending the 21st Interoperability Forum in person.  (Special treats for me were meeting a wonderful coworker, Gayane Markosyan, face-to-face and comparing hair lengths with Joe Daniels.) The 22nd Forum will be next Fall in Silicon Valley – be there or be square!

EDA standards blog The Standards Game
IPL Interoperable PDK Library pcells IPL Alliance
Open SystemC OSCI SystemC TLM transaction level modeling
Mike Santarini Rich Goldman
VMM Verification Methodology Manual open verification methodology OVM
Liberty Liberty standard .lib library standards

Next week, another bloggers Birds-of-a-Feather session will be held at ICCAD.  We will gather on Wednesday, November 12, from 4-6pm at the Doubletree hotel in San Jose, California.  The event will be in the Fir ballroom, and everyone is welcome.  Be sure to come – you don’t have to register for the conference. 

There are so many stories about blogging in the standards game that I’m not sure what I’m going to talk about in my 3-minute, 3-slide timeslot.  Is there anything you’re interested in hearing from me?  Post your comments below and I will certainly consider your suggestions.

I hope to meet many of you at what should be an interesting and interactive event.

EDA standards blog The Standards Game
ICCAD bloggers BoF birds of a feature

I don’t know about you, but I’ll be glad when the 2008 U.S. elections are over.  I mailed in my ballot this week and am now immune from those working hard to sway my vote.  I am honored and grateful to live in America, and I hope for a healthy, reunified country with global consciousness in 2009.

In The Standards Game, there is another important ballot underway: IEEE P1801, formally known as the “Standard for Design and Verification of Low Power Integrated Circuits”.  You may know this standard as UPF, the Unified Power Format, which was approved as an Accellera standard in February, 2007.  I’ve written about this standard in previous posts, describing its technical advantages and openness, plus the desire for a single industry standard.

The reason for UPF’s long official name in the IEEE is to distinguish it from other standards with the word “power” in their title.  As I might have mentioned, I’m a member of a couple of committees in the IEEE that approve standards in a wide range of electrical and electronic engineering fields.  I fondly remember one of my fellow committee members telling me that “low power” to him meant anything below 25,000 volts.  We certainly wouldn’t want a nuclear power plant generating the kind of low power that we think of in the semiconductor industry.

Low power IC design continues to be an imperative to support modern electronic product requirements.  The UPF/IEEE P1801 standard provides an open foundation for low power design solutions.  Leading suppliers of these solutions have built and are building tools and flows around UPF. 

UPF 1.0 from Accellera has been in real-world use, which has given users and EDA tool developers insights into ways to polish and enhance it within the IEEE P1801 Working Group. Oversights, ambiguities, verbosity, and backward compatibility have been addressed.  Enhancements have been made which include customer requirements that are new and some that were previously held for the next version.  Advanced power management solutions have been devised, and user interface improvements have been implemented.  

The resulting draft standard is now ready to receive the stamp of approval from the IEEE Standards Association.  Once it’s through the process, the “P” (which stands for “project”) will be dropped from UPF’s moniker and it will be simply, IEEE Standard 1801.

Finally, some very good news from the Si2 Low Power Coalition (the owner of CPF’s evolution) was delivered to the P1801 Working Group: the CPF 2.1 roadmap includes noteworthy efforts towards interoperability with P1801.  CPF, I’m sure you know, is an alternate format for describing low power design intent.

Congratulations to the IEEE P1801 Working Group as your draft standard goes through its balloting.  Everyone will be a winner in this particular election.

EDA standards blog The Standards Game
Unified Power Format UPF CPF Accellera IEEE standards IEEE P1801 low power standard