There’s a big world of standards out there beyond electronic design automation. It’s fascinating and changing, and its nature is relevant to our smaller world of EDA. In this post, I’m going to give you a view into a new paradigm that’s emerging for international standards. I’d like to hear your perspective.

To state the obvious (at least I hope it’s obvious by now), standards continue to create new markets, fuel industry growth, and protect people’s safety and health. Saying that the world revolves around standards is an exaggeration, but there’s no denying their value.

Standards have become universal, crossing country boundaries and resulting in multi-national collaboration, development, adoption, and maintenance. Traditionally, a standard gains global relevance when a national body – which represents its individual country’s interests – formally adopts it. This means the national body is a standards broker between its country’s industries and consumers. It brings relevant, internationally recognized standards to its economy as it deems appropriate. There are several advantages to this model including scrutiny, consensus, and coordination.

Industries are now global in nature. The pressures that today’s global industries face continue to intensify: time-to-market, competitive pricing, rapid technology advancements, and insatiable consumers. And they need standards to support them.

Industry will find a way to obtain the standards they need, when they need them. The traditional model for globally-adopted standards via national bodies is certainly a viable and proven way of doing so. And yet, an interesting new paradigm is emerging as well.

The global relevance of a standard is being determined by industries themselves –through adoption by companies in their products and services, and by the consumers who purchase those products and services. These standards can be ones recommended by the national body standards brokers. Or they can be ones from grass-roots, international consortia or simply international industry collaboration. Industry will choose the standards that serve it best. Enter the new global standards paradigm.

In future posts, I’ll give examples of the new paradigm and tell you how the IEEE Standards Association is positioned to embrace the changing world of standards, becoming irresistible to industry.

(Thanks to Steve Mills, President of the IEEE Standards Association for his insights and leadership.)

This year’s SNUG Silicon Valley is shaping up to be one of the best yet with another outstanding program in store for our customers. SNUG – the Synopsys Users Group conference – is Silicon Valley’s largest technical conference and one of Synopsys’ premier events. This year, it will take place at the Santa Clara Convention Center and kicks off Monday, March 26, 2012. I hope to see you there.

You might not realize that SNUG is Silicon Valley’s largest technical conference where the program is designed by engineers for engineers. SNUG provides users of Synopsys’ design tools and technology with an open forum where they can exchange ideas, discuss design challenges, and explore solutions. Today, there are 15 SNUG conferences worldwide that draw 9,000+ customers from more than 900 companies. For more information regarding future SNUG conferences, please refer to our World Wide Calendar on the SNUG website.

This year’s conference in Silicon Valley will feature more than 100 technical presentations as well as keynotes from leaders who are setting the tone for global design innovation. It’s also an opportunity for our customers to connect with Synopsys executives, our design ecosystem partners, and more than 2,000 members of the local design engineering community. Here is a preview of this year’s SNUG Conference-at-a-Glance.

SNUG Technical Chair John Busco, design Implementation manager at NVIDIA and one of the semiconductor & EDA industry’s first bloggers (here’s a link to his blog), will provide the opening welcome to the conference. He’ll introduce Aart de Geus, CEO & Chairman of the Board at Synopsys, who will deliver his keynote address, “Critical Mass, Systemic Complexity and Innovation: Catalysts for Designing Change.” John Cornish, ARM Executive Vice President and General Manager of ARM’s System Design Division, headlines Tuesday’s program with his keynote, “Partnering for Low Power,” where he will discuss next-generation process and the need for a system approach. Chenming Hu, Professor Emeritus at the University of California, Berkeley and former TSMC CTO, will deliver the technology keynote on Wednesday morning, “3D FinFET – New Structure Rejuvenates the Transistor!”

SNUG Silicon Valley keynote speakers: (from left) Aart de Geus, Synopsys, John Cornish, ARM, and Chenming Hu, University of California, Berkeley.

The technical program includes sessions related to low power, high performance, and embedded processor design, as well as design productivity and advanced design technology topics. In addition, the IP Summit, a special program designed for customers considering the use of IP to improve their productivity and design quality, will also be featured on Wednesday, March 28.

The Designer Community Expo (DCE) event will be returning to SNUG Silicon Valley as well. I particularly like this event because it grew out of an interoperability event that my team created. DCE is a unique opportunity for customers to meet Synopsys technology experts and our design community partners from across the electronics industry. Customers will be able to visit seven different design communities and see how more than 60 ecosystem partners are working with Synopsys to solve common design challenges.

If you are a Synopsys customer and wish to attend SNUG Silicon Valley, you will need to register on-site if you have not already registered.

I hope you enjoy another great SNUG in Silicon Valley.

I don’t often write about standards from the perspective of semiconductor IP. I leave that to my esteemed colleagues like Eric Huang (To USB or Not to USB) and Navraj Nandra (The Eyes Have It). I do, however, think about the importance of standards for IP fairly often. Here are some of those thoughts.

There are at least six ways that standards benefit IP. If you can think of more, bring it on!

IP is created using standards. Implementation and verification of an IP block requires standard languages and formats such as SystemVerilog (IEEE Std. 1800) and UPF (IEEE Std. 1801). Testbenches that accompany IP are written in a standard language like SystemC (IEEE Std. 1666).

Quality standards can help IP consumers determine if the IP they purchase meets the level of quality they require. The IP quality standard with the fancy name, “1734-2011 – IEEE Standard for Quality of Electronic and Software Intellectual Property Used in System and System on Chip (SoC) Designs”, is once such standard.

A standard can be implemented (and often is) as an IP block. USB, SATA, HDMI and many other interfaces are widely-used standards. They become real product features when their IP implementations are included in the products’ electronics.

The IP’s IP can be protected with standards. (OK, that was a little silly.) IP is encrypted by each IP vendor to protect it from being reverse-engineered or copied. Different vendors use different encryption, which can prevent IP from different vendors from talking to each other. A working group in the IEEE Standards Association is creating a standard with another fancy name, “P1735 – Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP)”. This standard will be able to help interoperability by providing a “generic set of embeddable markup syntax suitable for IP protection and rights management of arbitrary text files”. (That’s the description from the working group’s project plan.)

Speaking of interoperability, maybe one of the most important ways that standards help IP. An SoC design can have many IP blocks that need to communicate with each other and with custom portions of the design. I recently saw a list of standard design languages that are being used for SoCs. I shouldn’t have been surprised, but I was. The list included: C, C++, Verilog, VHDL, SystemVerilog, SystemC, e, OpenVera, and PSL. That’s a lot of standards. With mixed-language IP blocks in a single design, an obvious problem arises. The solution is a new standard based on an old one. Enter IP-XACT, “1685-2009 – IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows”. (Fancy.) It allows IP written in different languages to interoperate because it uses XML. What’s cool about XML is that it’s an internet standard, created and maintained by the World Wide Web Coalition (W3C). And it’s just plain text. IP-XACT is an elegantly simple standard to solve a big problem.

Ultimately, standards help reduce the cost of developing IP and speed its time to market. That’s definitely the most important way standards bring value to IP.

For the third (second consecutive) time, I’m honored to be the General Chair of the Design and Verification Conference. This year’s DVCon promises to bring you another valuable, technically-focused program that can help you with your complex design and verification projects.

DVCon is sponsored by Accellera Systems Initiative and has its roots in users’ groups for the Verilog and VHDL standards. Because standards continue to be vital (pun intended – first person to comment below on why it’s a pun will get a free coffee from me) to the IC design and verification process, the DVCon program includes sessions on key standards such as UVM, SystemC, UPF, and IP-XACT. Update: UCIS, too.

DVCon has continued to grow over the years, with its secret to success being its mission to bring the best technical papers and tutorials to its targeted audience: IC design and verification engineers. The Technical Program Chair, Ambar Sarkar, and Tutorials Chair, Stan Krolikoski – along with their qualified committee members – have worked hard to bring you the best content.

Keeping with tradition, this year’s keynote will be delivered by Dr. Aart de Geus, our fearless leader at Synopsys. If you’ve ever heard him speak, you know that he’s charismatic and inspiring. If you haven’t heard him speak, you’re in for a treat.

We made a positive change in the schedule so that the technical program and exhibits do not overlap. You’ll be able to visit the exhibits, see the vendors’ wares, and collect tchotchkes without missing a technical session. There will also be lunches, breakfast, and hors d’oeuvres & drinks to keep your stomach full and mind sharp (well, except for the drinks).

A unique activity at DVCon is when attendees get to vote for the best paper. Unlike other conferences where the best paper is chosen by committee, DVCon lets the audience decide. The voting system is automated (we used to tally paper ballots, believe it or not) and prevents stuffing the ballot box. Be sure to participate and let your opinion be counted.

You can test your knowledge with this clever quiz by Peggy Aycinena. Post your bragging rights on her article. Then, register for DVCon and enjoy the conference.

The IEEE Standards Association is always looking for interested people to participate in their working groups and governance committees. It can be an interesting and rewarding experience if you and your company are willing and able to invest a bit of time and money (not excessive amounts, in my experience). It’s a positive side of the standards game.

Presently, there’s a search underway for people who’d like to join the Corporate Advisory Group (CAG) in 2013-2014, which is all about IEEE’s entity-based standards. Examples of these standards in the electronic design automation industry are SystemVerilog, UPF, and SystemC. Clearly these are important standards that continue to benefit us broadly. I was a member of the CAG for several years and thoroughly enjoyed it.

Here’s more information about being a member of the CAG (copied from the IEEE-SA’s Call for Candidates). If you are interested, I’m happy to help you submit your information to the IEEE-SA. You can post a comment below, email me, send a message to me via LinkedIn, or send me a tweet. By now, I think it’s pretty easy to find me.

CAG responsibilities:

- Representing corporate member insight and guidance on needs, interest, vision, products, and services provided by the IEEE
- Establish the CAG as the recognized conduit for corporate perspectives
- Serves as advocate for IEEE
- Promotes and advocates new work in the IEEE-SA in all areas of the standards life cycle
- Promotes corporate representation, membership, and entity-based activities
- Facilitates industry feedback on present and proposed methods and tools provided for development of standards and related products
- Provides sponsorship, as appropriate, and sponsorship liaison for entity-based projects
- Advises on direction of IEEE-SA Corporate Program, including budget

Candidates must be interested in managing the development of industry standards and must hold strategic positions at corporations that are at least Basic Entity Members of the IEEE-SA (or that are willing to join).

If you would like to be considered for the 2013-2014 IEEE-SA Corporate Advisory Group, please note the following rules that apply to any potential candidate.

The deadline to respond is 15 May 2012.

The slate of candidates will be forwarded to the IEEE-SA Board of Governors Nominations and Appointments Committee (N&A) for its review later in the year, with a final decision on the candidate slate to be made by the IEEE-SA Board of Governors.

Rules for IEEE-SA CAG membership:

1. The time commitment is 3-6 meetings in 2013.
The 2012 calendar is located at http://standards.ieee.org/about/sasb/2012calendar.pdf. That will give you an idea of what to expect. The 2013 calendar has not been finalized yet.
Attendance is expected at all meetings.
2. This is a non-funded position.  You are expected to fund your own travel.
3. You must have an email address, web access, and a laptop computer to bring to the meeting.
Policies and Procedures related to the CAG are located at http://standards.ieee.org/develop/policies/sa_opman/sect5.html#5.3
Corporate Program information located at http://standards.ieee.org/develop/corpchan/index.html

I hope you’ll consider this opportunity. I think it would be great to work with you. BTW, “funding your own travel” usually means “your company funds your travel”. Let me know if you want more information. I’m happy to share my experiences with the IEEE Standards Association.

We are celebrating our 25th anniversary at Synopsys. You’ll see “25 years of enabling innovation” throughout this year. As part of recognizing our anniversary, we’re holding a trivia contest which will continue through December 2012. No doubt there will be a standards question or two.

We’ll post a question – two each month – and the first person to post the correct answer will win a $40 Amazon gift card.

You can play two ways, on our Facebook page and through Twitter.

On our Facebook page:

• If you’re not already, become a fan (click “Like” on www.facebook.com/synopsys)
• Watch your Facebook feed for our trivia questions to be posted
• Post your answer in the comment area under the trivia question

Through Twitter:

• If you’re not already, follow us on Twitter (click “Follow” on www.twitter.com/synopsys)
• Watch your Twitter timeline for trivia questions posted by @synopsys
• Tweet your answer to @synopsys

The winner of each question will be announced right away via Facebook and Twitter.

Read the full contest rules here.

The contest is underway. The first question was, “What was Synopsys’ original name when the company was founded?” The answer is, “Optimal Solutions”. (Did you know that?)

For more trivia about Synopsys and our history, visit our timeline.

Play and enjoy the game! (Almost forgot, no Synopsys employees, please.)

By now, you’ve probably seen the announcement of Accellera and Open System C Initiative (OSCI) merging to form a new, unified organization called Accellera Systems Initiative. This marks the next chapter in the history book of EDA standards organizations.

A decade ago, I was part of the core team that brought VHDL International (VI) and Open Verilog International (OVI) to form Accellera. VI and OVI were successful in their own right in the promotion and adoption of their respective HDLs (VHDL and Verilog). One could say that the formation of Accellera was due to the industry’s desire that HDLs had to grow further to help address verification, test, and power issues. Part of the truth, though, is that we were duplicating efforts and paying too much for two organizations. I’ll never forget going to a VI board meeting one day and an OVI board meeting the day after. Many of the same people were in both meetings, but some of them switched their viewpoints. I called them out for arguing with themselves.

Accellera’s desire to provide much-needed standards was realized with SystemVerilog, Open Verification Library (OVL), Open Compression Interface (OCI), Unified Power Format (UPF) and Universal Verification Methodology (UVM). Accellera then merged with The SPIRIT Consortium to expand the scope of language-based standards activity to include IP standards. Today, IP-XACT efforts under Accellera are helping integrate use of IP and its meta-data into various standards such as UVM. This is a classic example of collaboration among adjacent standards that benefits the user community with improved productivity and provides business opportunities for tool and IP vendors.

Here is some trivia about the merger that you won’t find in the announcement:

- Most of the Board makeup is the same as before (7 of 9 OSCI board members were also Accellera board members). That should bring continuity and easier integration of things like Policies and Procedures.

- There is an increase in the number of associate members. This brings the opportunity for broader collaboration and participation in future standards work.

- Logistics and infrastructure will continue to be provided by the highly capable and experienced people who’ve worked for both organizations for decades.

- Kavi continues to provide the online platform.

- Members will save money on dues and get more benefits. There, I said it.

- There is a good balance between users and vendors. Accellera Systems Initiative is not dominated by EDA companies.

- Accellera Systems Initiative will not be called ASI. That would be confusing.

- The idea of merging the two organizations came up four years ago.

As the Accellera and OSCI communities come together under a single umbrella, I believe the new organization will remain focused on the fundamental premise of EDA standards – interoperability between tools to help build robust design and verification flows. Portability of a design across multiple tools may be desirable (e.g., switching from one functional simulator to another), but it’s often not practical. It’s the ability to take the design through successive stages of refinement and validation that makes the standards most valuable.

I would like to see Accellera Systems Initiative bring the industry even more collaboration and the platform for improved interoperability across system and chip design tools in coming years. And I’d like to invite you to participate.

A final aspect on why Synopsys participates heavily in technical industry standards is one that is often missed (or dismissed): Standards enable innovation. Many people confuse standardization with stifling innovation because standards provide precise specifications. They mistakenly believe that once a standard is defined (and most importantly, accepted) in the industry, all other alternatives are doomed and no further innovation is possible. This cannot be farther from the truth. In fact, having a standard – particularly an open standard – allows the entire industry to come to an agreement about common abstractions, representations, and/or terminologies so that the communication of certain problems and solutions becomes easier and less susceptible to misinterpretation. Suppliers such as Synopsys then have a foundation upon which to build products that embody the most modern, collective thinking of the industry.

Electronic design standards such as Hardware Description Languages (HDLs) have fueled innovation for decades in the semiconductor industry. These language standards raised the level of design abstraction to help enhance productivity – that was the benefit in the early days when the industry was migrating away from schematic-based design. Further, the HDLs – initially Verilog and VHDL – allowed designers to think in terms of functions rather than structures, thereby enabling design sizes to move from thousands of gates to millions of gates. The innovations that followed came in many forms – from design and analysis tools to new methodologies and global teams working around the clock on large projects. None of this would have been possible without a common, precise language to describe electronic circuits.

More recently, the SystemVerilog HDL has allowed us to think in terms of object-oriented verification environments for the ever-increasingly complex system-on-chip (SoC) designs. The success of a “reuse paradigm”, both for design and verification building blocks and the SoCs that are designed with them, is due in large part to the standardization of HDLs, HDL-based methodologies, and other technical standards.

From a different perspective, standards enable innovations to be developed on top of maturing technologies rather than reinventing the wheel. This increases the rate of innovation – a far cry from stagnation.

In addition to HDLs, Synopsys and our customers are also beneficiaries of technical standards such as the well-known USB, Wi-Fi, and PCI. and other communication protocols/interfaces. As a leader in the IP building block business, we are able to provide standards-based design and verification IP to help our customers accelerate their product schedules. Availability of standards-based, verified components allows the precious skilled engineering resources to be focused on building innovative and differentiated products instead of reinventing the wheel of implementing standard interfaces. Our participation in the groups that create and maintain these standards means we supply IPs that are compliant with the approved specifications, and we help enable interoperability between devices adhering to the corresponding standard.

From our very beginning, Synopsys’ business has benefited from using HDL standards as input to our tools, be it synthesis or simulation. Working with our customers and the entire semiconductor ecosystem, we have developed standards-based tools and methodologies to help ensure that each design moves from concept to silicon and then into a system (an end product) in the most efficient manner. We continue to invest in standardization efforts, lead with new and innovative technologies, and collaborate with customers, partners, and competitors alike to build strong platforms that enable the advancement of innovation.

Active participation in industry standardization activities requires a long-term vision and commitment, and the benefits are tangible. We have this, and that’s why we do it.

In addition to growing the market (part 1 of this series) and establishing and maintaining technology leadership (part 2), standards promote the discovery of complete solutions in collaboration with key industry players. These collaborative solutions benefit customers, of course, by providing the best overall result which is developed as broadly as possible. Perhaps less obvious is that collaborative solutions also benefit suppliers like Synopsys. Drawing not only upon technology contributions from customers and competitors alike, but also from their expertise, allows us to create products that address a bigger set of challenges being faced by today’s advanced system-on-chip designers.

Whether our technology alone is being donated to be considered as part of a standard or it is one of several contributions, the goal is always to look for ways a new standard will help solve a wide range of problems. As a solutions provider, we certainly have insight into some of the use models that will benefit from the new standard. Often times, however, other participants in the standards development process bring additional requirements for the new standard to support use models that were previously not considered.

For example, Synopsys made the Liberty format for technology library modeling – originally known as .lib – an open standard more than a decade ago. Following that, some of the very first updates to Liberty came from recommendations by Cadence Design Systems. As process technology continued to move ahead from 180 nanometer to 90 nanometer towards 14 nanometer, many new features were added to the Liberty format to represent corresponding abstractions for design and analysis tools. Contributors to its upgrades included IC designers, EDA tool suppliers, and library developers.

Currently evolving under the IEEE’s Industry Standards & Technology Organization (IEEE-ISTO), the format continues to progress along with the technology it supports. Overseeing its evolution is the Liberty Technical Advisory Board (LTAB), a group of experts with a vested interest in maintaining the usefulness and robustness of the Liberty format.The group continues to tap into Synopsys’ – and others’ – expertise which is made readily available. Most recently, the group discussed and approved several new features to help model low-power cells, which are critical to the advancement and sales of mobile devices.

The collaborative effort among semiconductor foundries, fabless design houses, semiconductor IP providers, and EDA tool vendors (several in addition to Synopsys) is continuing to benefit the entire industry. It is also helping Synopsys maintain close ties with the entire semiconductor ecosystem to better understand upcoming requirements and challenges – giving us an opportunity to be the first to provide innovative solutions.

Technology leadership is a multi-faceted undertaking – one that requires continuous effort in several areas. One of these important areas is technical standards. It may or may not come as a surprise, but cooperating on and contributing to industry standards activities can further a company’s technical leadership.

At my company, we collaborate with a wide range of players in the industry on standards issues. This includes competitors, partners, and customers – typically in a Standards Development Organization (SDO) such as the IEEE Standards Association or Standards-Setting Organization (SSO) like Accellera.

Through such participation, we often find that our endeavors to solve our customers’ problems are exactly the same as our competitors’. In fact, at times, the customers who are participating in standards activities are asking us to solve the same problem as they ask the other EDA tool suppliers. In many cases, standards-based collaborative efforts are far more efficient overall than having one vendor working directly with each customer.

The Universal Verification Methodology (UVM) and Unified Power Format (UPF) under Accellera (which is now IEEE Std. 1801) are great examples of standards helping solve much larger problems across the broad industry than what individual companies could do on their own.

These standards successes (and many others) led with technology donations from Synopsys, such as the core of SystemVerilog, the register package in UVM, and several low-power technologies for UPF. Donation (in standards parlance, “contribution”, to differentiate it from money) of production-proven technologies helps align the EDA  tool developers and IP providers with the customers in the most effective and expedient manner. As customers and non-customers become aware of the public standards based on our technology, not only does it continue to build Synopsys’ technical leadership and respect for our technologists, but it also provides the opportunity for adoption of our tools and methodologies because they are standards-compliant. This is yet another good reason why we at Synopsys continue to be actively involved in standards activities.