We are celebrating our 25th anniversary at Synopsys. You’ll see “25 years of enabling innovation” throughout this year. As part of recognizing our anniversary, we’re holding a trivia contest which will continue through December 2012. No doubt there will be a standards question or two.

We’ll post a question – two each month – and the first person to post the correct answer will win a $40 Amazon gift card.

You can play two ways, on our Facebook page and through Twitter.

On our Facebook page:

• If you’re not already, become a fan (click “Like” on www.facebook.com/synopsys)
• Watch your Facebook feed for our trivia questions to be posted
• Post your answer in the comment area under the trivia question

Through Twitter:

• If you’re not already, follow us on Twitter (click “Follow” on www.twitter.com/synopsys)
• Watch your Twitter timeline for trivia questions posted by @synopsys
• Tweet your answer to @synopsys

The winner of each question will be announced right away via Facebook and Twitter.

Read the full contest rules here.

The contest is underway. The first question was, “What was Synopsys’ original name when the company was founded?” The answer is, “Optimal Solutions”. (Did you know that?)

For more trivia about Synopsys and our history, visit our timeline.

Play and enjoy the game! (Almost forgot, no Synopsys employees, please.)

By now, you’ve probably seen the announcement of Accellera and Open System C Initiative (OSCI) merging to form a new, unified organization called Accellera Systems Initiative. This marks the next chapter in the history book of EDA standards organizations.

A decade ago, I was part of the core team that brought VHDL International (VI) and Open Verilog International (OVI) to form Accellera. VI and OVI were successful in their own right in the promotion and adoption of their respective HDLs (VHDL and Verilog). One could say that the formation of Accellera was due to the industry’s desire that HDLs had to grow further to help address verification, test, and power issues. Part of the truth, though, is that we were duplicating efforts and paying too much for two organizations. I’ll never forget going to a VI board meeting one day and an OVI board meeting the day after. Many of the same people were in both meetings, but some of them switched their viewpoints. I called them out for arguing with themselves.

Accellera’s desire to provide much-needed standards was realized with SystemVerilog, Open Verification Library (OVL), Open Compression Interface (OCI), Unified Power Format (UPF) and Universal Verification Methodology (UVM). Accellera then merged with The SPIRIT Consortium to expand the scope of language-based standards activity to include IP standards. Today, IP-XACT efforts under Accellera are helping integrate use of IP and its meta-data into various standards such as UVM. This is a classic example of collaboration among adjacent standards that benefits the user community with improved productivity and provides business opportunities for tool and IP vendors.

Here is some trivia about the merger that you won’t find in the announcement:

- Most of the Board makeup is the same as before (7 of 9 OSCI board members were also Accellera board members). That should bring continuity and easier integration of things like Policies and Procedures.

- There is an increase in the number of associate members. This brings the opportunity for broader collaboration and participation in future standards work.

- Logistics and infrastructure will continue to be provided by the highly capable and experienced people who’ve worked for both organizations for decades.

- Kavi continues to provide the online platform.

- Members will save money on dues and get more benefits. There, I said it.

- There is a good balance between users and vendors. Accellera Systems Initiative is not dominated by EDA companies.

- Accellera Systems Initiative will not be called ASI. That would be confusing.

- The idea of merging the two organizations came up four years ago.

As the Accellera and OSCI communities come together under a single umbrella, I believe the new organization will remain focused on the fundamental premise of EDA standards – interoperability between tools to help build robust design and verification flows. Portability of a design across multiple tools may be desirable (e.g., switching from one functional simulator to another), but it’s often not practical. It’s the ability to take the design through successive stages of refinement and validation that makes the standards most valuable.

I would like to see Accellera Systems Initiative bring the industry even more collaboration and the platform for improved interoperability across system and chip design tools in coming years. And I’d like to invite you to participate.

A final aspect on why Synopsys participates heavily in technical industry standards is one that is often missed (or dismissed): Standards enable innovation. Many people confuse standardization with stifling innovation because standards provide precise specifications. They mistakenly believe that once a standard is defined (and most importantly, accepted) in the industry, all other alternatives are doomed and no further innovation is possible. This cannot be farther from the truth. In fact, having a standard – particularly an open standard – allows the entire industry to come to an agreement about common abstractions, representations, and/or terminologies so that the communication of certain problems and solutions becomes easier and less susceptible to misinterpretation. Suppliers such as Synopsys then have a foundation upon which to build products that embody the most modern, collective thinking of the industry.

Electronic design standards such as Hardware Description Languages (HDLs) have fueled innovation for decades in the semiconductor industry. These language standards raised the level of design abstraction to help enhance productivity – that was the benefit in the early days when the industry was migrating away from schematic-based design. Further, the HDLs – initially Verilog and VHDL – allowed designers to think in terms of functions rather than structures, thereby enabling design sizes to move from thousands of gates to millions of gates. The innovations that followed came in many forms – from design and analysis tools to new methodologies and global teams working around the clock on large projects. None of this would have been possible without a common, precise language to describe electronic circuits.

More recently, the SystemVerilog HDL has allowed us to think in terms of object-oriented verification environments for the ever-increasingly complex system-on-chip (SoC) designs. The success of a “reuse paradigm”, both for design and verification building blocks and the SoCs that are designed with them, is due in large part to the standardization of HDLs, HDL-based methodologies, and other technical standards.

From a different perspective, standards enable innovations to be developed on top of maturing technologies rather than reinventing the wheel. This increases the rate of innovation – a far cry from stagnation.

In addition to HDLs, Synopsys and our customers are also beneficiaries of technical standards such as the well-known USB, Wi-Fi, and PCI. and other communication protocols/interfaces. As a leader in the IP building block business, we are able to provide standards-based design and verification IP to help our customers accelerate their product schedules. Availability of standards-based, verified components allows the precious skilled engineering resources to be focused on building innovative and differentiated products instead of reinventing the wheel of implementing standard interfaces. Our participation in the groups that create and maintain these standards means we supply IPs that are compliant with the approved specifications, and we help enable interoperability between devices adhering to the corresponding standard.

From our very beginning, Synopsys’ business has benefited from using HDL standards as input to our tools, be it synthesis or simulation. Working with our customers and the entire semiconductor ecosystem, we have developed standards-based tools and methodologies to help ensure that each design moves from concept to silicon and then into a system (an end product) in the most efficient manner. We continue to invest in standardization efforts, lead with new and innovative technologies, and collaborate with customers, partners, and competitors alike to build strong platforms that enable the advancement of innovation.

Active participation in industry standardization activities requires a long-term vision and commitment, and the benefits are tangible. We have this, and that’s why we do it.

In addition to growing the market (part 1 of this series) and establishing and maintaining technology leadership (part 2), standards promote the discovery of complete solutions in collaboration with key industry players. These collaborative solutions benefit customers, of course, by providing the best overall result which is developed as broadly as possible. Perhaps less obvious is that collaborative solutions also benefit suppliers like Synopsys. Drawing not only upon technology contributions from customers and competitors alike, but also from their expertise, allows us to create products that address a bigger set of challenges being faced by today’s advanced system-on-chip designers.

Whether our technology alone is being donated to be considered as part of a standard or it is one of several contributions, the goal is always to look for ways a new standard will help solve a wide range of problems. As a solutions provider, we certainly have insight into some of the use models that will benefit from the new standard. Often times, however, other participants in the standards development process bring additional requirements for the new standard to support use models that were previously not considered.

For example, Synopsys made the Liberty format for technology library modeling – originally known as .lib – an open standard more than a decade ago. Following that, some of the very first updates to Liberty came from recommendations by Cadence Design Systems. As process technology continued to move ahead from 180 nanometer to 90 nanometer towards 14 nanometer, many new features were added to the Liberty format to represent corresponding abstractions for design and analysis tools. Contributors to its upgrades included IC designers, EDA tool suppliers, and library developers.

Currently evolving under the IEEE’s Industry Standards & Technology Organization (IEEE-ISTO), the format continues to progress along with the technology it supports. Overseeing its evolution is the Liberty Technical Advisory Board (LTAB), a group of experts with a vested interest in maintaining the usefulness and robustness of the Liberty format.The group continues to tap into Synopsys’ – and others’ – expertise which is made readily available. Most recently, the group discussed and approved several new features to help model low-power cells, which are critical to the advancement and sales of mobile devices.

The collaborative effort among semiconductor foundries, fabless design houses, semiconductor IP providers, and EDA tool vendors (several in addition to Synopsys) is continuing to benefit the entire industry. It is also helping Synopsys maintain close ties with the entire semiconductor ecosystem to better understand upcoming requirements and challenges – giving us an opportunity to be the first to provide innovative solutions.

Technology leadership is a multi-faceted undertaking – one that requires continuous effort in several areas. One of these important areas is technical standards. It may or may not come as a surprise, but cooperating on and contributing to industry standards activities can further a company’s technical leadership.

At my company, we collaborate with a wide range of players in the industry on standards issues. This includes competitors, partners, and customers – typically in a Standards Development Organization (SDO) such as the IEEE Standards Association or Standards-Setting Organization (SSO) like Accellera.

Through such participation, we often find that our endeavors to solve our customers’ problems are exactly the same as our competitors’. In fact, at times, the customers who are participating in standards activities are asking us to solve the same problem as they ask the other EDA tool suppliers. In many cases, standards-based collaborative efforts are far more efficient overall than having one vendor working directly with each customer.

The Universal Verification Methodology (UVM) and Unified Power Format (UPF) under Accellera (which is now IEEE Std. 1801) are great examples of standards helping solve much larger problems across the broad industry than what individual companies could do on their own.

These standards successes (and many others) led with technology donations from Synopsys, such as the core of SystemVerilog, the register package in UVM, and several low-power technologies for UPF. Donation (in standards parlance, “contribution”, to differentiate it from money) of production-proven technologies helps align the EDA  tool developers and IP providers with the customers in the most effective and expedient manner. As customers and non-customers become aware of the public standards based on our technology, not only does it continue to build Synopsys’ technical leadership and respect for our technologists, but it also provides the opportunity for adoption of our tools and methodologies because they are standards-compliant. This is yet another good reason why we at Synopsys continue to be actively involved in standards activities.

An analogy of “three big dogs hovering over a bowl of dog food” has been used to explain the business challenges of the EDA industry. This oft-cited quote is attributed to Cadence’s founder and first CEO, Mr. Joe Costello, debating how EDA had become a fixed-pie industry on a panel at DAC in 1995. For history buffs, amusingly, the response from Synopsys’ CEO – then and now – Dr. Aart de Geus, was “If you think of yourself as a dog, you only deserve dog food!” Surely, the quote was highlighted out of context; but it leaves one with the nagging question of how does an industry go about growing the pie rather than redistributing the fixed pie? Of course, there are many well-proven business strategies for doing so, and standards is certainly one of them.

An ecosystem built around technologies that are based on support for industry standards has many advantages. Even while pointing to Apple’s success through a strategy of controlling the entire ecosystem, one must realize that all those consumer devices connect through well-known standards such as Wi-Fi (IEEE 802.11n) and USB, and the iPhone connects through different phone carriers. It will also be interesting to watch whether Android can topple Apple again like the IBM PC compatibles did decades ago.

The point is that standards – specifically, standards-based interoperability – enable two or more industries/industry segments to interact with each other to provide a desired and complete solution, thereby growing and benefiting each of the industries.

However, the mere creation or existence of a standard does not by itself grow the market. In fact, until it is widely adopted, it is difficult to say whether there is actually a standard or not. To produce an actual standard, adoption of the standard needs to be shepherded through product introductions, education, books, conferences, white papers, and so on. It’s also necessary to nurture new business models, forge partnerships, and continue on an evolutionary roadmap for a period of time before it becomes apparent that the use of certain technology has become a standard. The length of this time varies by industry and degree of difficulty to implement the standard, and in the EDA industry it is usually at least 2 years.

A good example of an EDA standard that grew the pie is SystemVerilog. Based on contributed technologies, it took (arguably) about 3 years to complete and have serious adoption begin. At present, there are at least 125 products, solutions, and training offerings that make up the SystemVerilog-enabled market.

Feeding more dogs with a bigger pie makes everyone – suppliers, customers, and investors – happier.

After a long summer break and time for a blogging platform upgrade, The Standards Game is back in action. My blog may have had a quiet period, but the world of standards kept on turning. It’s hard to believe that Fall is here already and so many interesting events took place during The Standards Game’s vacation.

Here are a few highlights of what happened over the past few months.

Accellera and OSCI announced their plans to merge into a single organization. The new organization will combine the experience and resources of both bodies to broaden its benefit to the electronics industry. System-level design – and the standards that support it – is an integral part of System-on-Chip (SoC) design. A single standards-setting organization that addresses the interoperability requirements from the industry.

There was significant movement in the low-power standards arena. Si2 announced that they contributed relevant parts of the CPF 2.0 specification to the IEEE P1801 (UPF) working group, and  Cadence is also participating in the working group. “Convergence” is a term we’ve talked about for at least 4 years. I hope it will finally become a reality.

The Design Automation Standards Committee (DASC) held its annual election for officers. Each office is a two-year team, with two officers being elected each year. This year the positions of Chair and Vice-Chair were up for election. Stan Krolikowski was re-elected as DASC chair, and Yatin Trivedi was elected as Vice-Chair, Kathy Werner remains as Secretary and Victor Berman remains as Treasurer. (BTW, renewing and new members of DASC should pay their annuals dues before the end of 2011. At 40 $USD, it’s a bargain.)

Planning for DVCon 2012, which will include the latest in Accellera/OSCI standards, technical papers, industry-leader panels, and methodology tutorials, is well underway. Paper and panel selections are being finalized by the Techical Program Committee. Aart de Geus, CEO of Synopsys, will be the keynote speaker. (I’m the General Chair.)

Finally, the annual IEEE election was held and I was voted in as the 2012 President-Elect of the IEEE Standards Association. I will be the IEEE-SA President in 2013-14, at which time I will also have a seat on the Board of the IEEE itself. It’s going to be a great experience, I’m truly honored, and I’ll work hard to keep and increase the effectiveness of IEEE standards.

As always, I welcome your observations, ideas, and questions as we continue to participate in the standards game.

It’s been never-ending excitement in the standards game since September 2007 when this blog began. After nearly 4 years, it’s time for a short vacation from blogging. I’m certainly not leaving the standards arena. Instead, I’ll likely be doing even more with the IEEE Standards Association. I’m also starting to work with people who are entering the world of standards and are looking for advice and guidance.

I”ll be around in many places. Listen as I host interesting guests on Conversation Central. Follow me on Twitter. See what we’re up to on Synopsys’ Facebook page. Connect with me on LinkedIn.

In the Fall, I promise I’ll be back. There will be interesting standards topics to write about. Hint: IEEE 1801 (UPF) and CPF.

Have a great summer, everyone!

We have a great lineup of guests for you on Conversation Central at the 48th Design Automation Conference. Join us in the audience in the front of Synopsys’ main booth to see the shows and talk with the guests. If you’re not at DAC, you can watch the video sessions live-streamed to our Facebook page. See the schedule below.

Dubbed “The Voices of DAC”, all shows will be recorded and published afterward for listening and viewing at your convenience. You can find the shows on iTunes (or search the iTunes store for “Conversation Central”) and on our show notes site www.synopsys.com/blogs/conversationcentral. Additionally, video Conversation Central shows can be seen on Synopsys’ Facebook page www.facebook.com/SynopsysInc and Synopsys’ YouTube channel www.youtube.com/synopsystv.

In addition to Conversation Central, we’ll give you a unique networking card with a QR code for your LinkedIn profile. Use your card to connect with colleagues and friends during the cocktail receptions on Monday, Tuesday and Wednesday from 6 to 7pm on the Garden Terrace on level 2 of the San Diego Convention Center. Continue using your card to connect with people throughout DAC and afterward.

If you’re a fan of Twitter or would like to experiment with it, come play our Twitter Trivia game. There will be two ways to win:

- Pick up a game card in Synopsys’ booth and find secrets to tweet at special DAC events.

- Tweet @synopsys and/or tag tweets with #snps from June 5 through June 9. Be sure to include #48DAC in your tweets. That way, you can win even if you’re not at DAC!

Come to Synopsys’ booth anytime to get a free copy of the newest book from Synopsys Press, “Social Media Geek-to-Geek: Practical Insights for Technology Marketers”. The author, Kathy Schmidt Jamison, will sign your book on Monday at 4:30, Tuesday at 11:30, and Wednesday at 10:30.

Conversation Central schedule for the 48th DAC:

The 48th Design Automation Conference is almost here. Again, there will be several activities of interest for both those of you who want to learn about standards and those who regularly play the standards game.

Standards are very important to EDA and semiconductor design industry. For 12^th year, Synopsys is organizing The Standards Booth (#3328) at DAC where you will find Synopsys along with its partners demonstrating interoperable flows using industry standards. The four pods represent widely used standards from Accellera, IEEE, OSCI, IPL, and IEEE-ISTO. The Standards Booth will be located right next to Synopsys main booth, so it will be easy to find.

Of course, it won’t be only standards and interoperability talk in The Standards Booth. We’ll make this a lot of fun with “Prize Frenzy” where every half hour we’ll have a drawing for an iPod Nano. A different color iPod Nano every day. That’s a lot of Nanos. (Or is it Nanoes?) To win one of them, come to the booth and collect your game card. Visit all four pods in the booth, fill out a short questionnaire (really short), and you are on your way to all the excitement of the prize drawing – every half hour, enter as many times as you wish. How cool is that?

On Wednesday morning, come to Marriott (Marina Ballroom F) and attend Synopsys’ Interoperability Breakfast: “On Safari with Custom Design Interoperability & Interconnect Modeling Standards.” Listen to leading users talk about their experience with use of interoperable PDKs (iPDKs) and Interconnect Technology Format (ITF). We’ll also announce the recipient of this year’s Tenzing Norgay Interoperability Achievement Award.

I will be right next door, in Synopsys’ main booth, if you’d like to stop by and say hello. We’ll have “Meet the Bloggers” periodically in the Conversation Central area – left front corner as you face the booth.

To get you in the mood for The Standards Booth, listen to the theme song from the first ever Standards Booth, “My Flow’s in Jeopardy”.

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