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A couple of years ago we started looking at figuring out how to support analog functions on 28-nm processes, analog functions that had good performance over a wide range of process, voltage and enviromental variations.  One focus area was the audio CODEC. There are three main circuit blocks that limit how much an analog IP scales with process technologies:

• Active amplifiers and resistor ladders: Active amplifiers and resistive ladders are used in a multitude of volume controls and switches that mix different audio sources together. Active amplifier performance is limited by device matching characteristics. Reducing the area of the individual devices negatively impacts the device matching and significantly degrades the active amplifier performance. For this reason, active amplifiers in 28-nm process nodes are not significantly smaller in area than amplifiers with the same performance in 40-nm or 65-nm processes. In order to avoid any noticeable artifacts such as zip noise, the volume gain steps need to be below 1 dB. This requires the resistive ladder to have a large number of taps, which increases the overall area.
• Data converters: Most audio codecs are implemented with sigma-delta ADC and DAC circuits. The noise level in the switched capacitor circuits is inversely proportional to the capacitance. This puts a minimum capacitance value required for a given audio performance requirement, therefore, the capacitor area will not scale with process node. Further complicating matters, as the supply voltage reduces from 2.5 V (or 3.3 V) down to 1.8 V in 28-nm processes, in order to maintain the same dynamic range, the noise level must be reduced. The capacitors must increase in both area and capacitance.
• Output drivers: Large output currents must be delivered with low distortion. In order to support the large output currents needed to drive the headphones and loudspeakers, the output devices must be very large and will not scale with process technology. Similar to the data converter block, and as discussed in more detail below, the output driver circuit area and performance is impacted by the migration from 2.5 V to 1.8 V supplies.

Having evaluated these areas our engineering team were able to suppport these requirements in 28-nm. A more detailed write-up is published on

http://www.eetimes.com/design/audio-design/4238385/Integrating-audio-codecs-in-next-generation-SoCs-for-smartphones-and-tablets?Ecosystem=audio-design

Synopsys’ user group (SNUG) attracts about 3000 engineers over the three day event in San Jose. This year we will repeat the very successful “IP Summit” – a day devoted to designers and technology leaders. Topics relevent to today’s design challenges and expert opinions on future directions will be presented in a 60 to 90 minute tutorial format:

- Best practices on implementing memories and libraries

- Designing PCIe 3.0 Express

- RFID tagging technology

- Meeting quality of service for DDR controllers

- Creating an Audio IP subsystem

- Using synthesis tools to improve datapath quality of results

- Integrating USB 3.0

- Integrating MIPI

-The Role of IP in More Moore and More than Moore

Also TMSC’s Dr. Suk Lee  will present “The Impact of Process Migration on IP Design” key note, over lunch.

You’ll have the opportunity to hear from industry experts, ask questions and of course network.

Looking forward to seeing you there.

When: Wednesday March 28
Where: Santa Clara Convention Center

More details: : http://www.synopsys.com/IP/Pages/IPSummit2012.aspx

USB is one of those interfaces that you cannot live without. Charging your mobile device or transferring photos, music, powerpoint slides (usually in my case just before an important meeting) is the role of USB. It is the workhorse. It delivers. As files get bigger –  I heard about the Nokia phone that has a 41 megapixel camera http://abcn.ws/xXPiCp - about four times the resolution of my really good camera, the need for a faster USB to transfer these megapixel photos becomes necessary. USB 3.0 is that technology – tens times faster than your current USB. So over the last couple to three years there was lots of talk about USB 3.0 – and finally it happened http://bit.ly/zf99yw .

But what about the previous USB 2.0 generation? In many cases this still is the primary interface in consumer devices and our development and marketing teams at Synopsys have been busy in improving the power, performance and area in the latest 28-nm and 20-nm technologies. In terms of an ecosystem, compliance and interoperability requirements (remember this interface HAS to work), the USB implementers’ forum upped the ante and now require all new USB 2.0 products to demonstrate successful interoperability with various USB 3.0 hosts.  This evolution in the USB 2.0 Hi-Speed logo certification process from requiring successful tests with various USB 2.0 hosts to USB 2.0 and USB 3.0 hosts now just shows how important interoperability with USB 3.0 is becoming.

And it’s becoming more and more mobile oriented…

We call our product USB 2.0 picoPHY. The new features increase battery life and speed recharging in next generation mobile designs, such as smart phones and tablets. Also included is support for  the USB Battery Charger v1.2 standard and addition of low-power features such as aggressive power supply collapsing with high voltage interrupt signaling, and reduced core voltage in suspend mode.

So USB 3.0 is the future but there is plenty of innovation in USB 2.0 left.

Synopsys USB 2.0 test-chips

Silicon results in 28-nm and USB IF certification

Tomorrow I’ll be presenting at TSMC’s OIP (Open Innovation Program) on a topic regarding high performance analog and interface IP that is used in the latest smart phones, tablets and also the data centers. The idea of the talk was triggered by an article that I read about how the theoretical limit of Shannon’s Law is being reached and that Moore’s Law can be used to extend this bandwidth limit. What I’m presenting is that using the latest 28 nm and 20 nm technologies high performance analog and interface IP can be developed that can extend Shannon’s theoretical limit. If you cannot attend the talk, here’s the summary.

Extending Shannon's Limit?

What’s causing this bandwidth limit?

Mobile multimedia products such as smartphones and tablets are driving huge bandwidth requirements into the data centers. A rough order magnitude states that one server in the data center is needed to handle the traffic from every 600 smartphones or 122 tablets. By 2015, it is projected that 7.1 billion phones and tablets, will be sending 75 exabytes (one billion gigabytes) of internet traffic. To address these bandwidth limits, Moore’s Law is driving innovation at the system-on-chip (SoC) level with quad-core CPU’s running in excess of 1.5 GHz in 28 nm. In order to get data on and off the SoC, from the application processor to the base-band chip, high performance interfaces are used. Since the design and implementation challenges are significantly greater at 28 nm and below, SoC development teams are looking for ways to meet aggressive product cycles by implementing third party intellectual property (IP) for these interfaces. 

28-nm, 20-nm technology and IP

Being a consumer driven market, cost is a major factor for mobile multimedia products and SoC companies are using economies of scale afforded by 28 nm integration levels to build media processors to fit multiple personal computer and consumer electronic platforms. The interface IP needs include multi-port USB 2.0, USB 3.0, HSIC (high-speed inter-chip) which is derived from the USB protocol, PCI Express Gen. 1, SATA, HDMI Tx (to connect to high definition displays), MIPI CSI/DSI for camera and displays interfaces, Gigabit Ethernet and SD 4.0. Also, smartphone storage will exceed 100 GB in 2012 and this will require both throughput and capacity: USB “sync-n-go”, micro-USB, potentially UFS (universal flash storage) are likely candidates for this type of interface IP. The DRAM bandwidth is growing faster than any market segment: mDDR (mobile DDR) is being replaced by LPDDR2 this year. Audio codec’s and general purpose data converter IPs are also required. The low power variant of 28 nm technology (the POLYSION based LP, or the HKMG HPL) is the preferred choice with a 1.8 V gate oxide. Other important requirements include special power down modes.

On the other end, data centers or cloud computing is driving high-end IP requirements in 28HPM or 28HP processes. The data center backbone will use the 8 Gb/s PCIe 3.0 switches and these are used to connect to multi-channel 10 Gb Ethernet HBA (host bus adapters). The high-speed DDR3 memory interfaces are expected to operate at 2133 Mb/s supporting both RDIMM and LRDIMM – and these will eventually move to DDR4 2013.

How does TSMC’s OIP help in all of this?

TSMC’s Open Innovation Program (OIP) is an integral part of the collaboration between Synopsys and TSMC. For analog/mixed-signal IP this means access to early versions of design kits help reduce the adoption barrier for customers implementing next-generation SoC designs in the advanced process technologies.  By providing IP that meets the rigorous TSMC9000 certification standards, Synopsys and TSMC are enabling our mutual customers to reduce integration risk and system cost, while quickly ramping up into volume production

Flicking through an in-flight magazine this evening, my eye caught an ad with the title “Good-bye Sluggomorbus – Hello SuperSpeed USB” – it so happened I was on my way to a customer meeting to discuss – yes you got it – USB 3.0.

So the ad goes…”Sluggomorbus strikes when slow transfer rates make you wait for photos to upload…..symptoms include falling asleep, obscene gestures…”

Actually my meeting was to discuss the key considerations of integrating the USB 3.0 PHY into the customer’s chip, a topic that my readers would be interested in too.  So here goes… If you are thinking about USB 3.0 PHY integration the following decisions need to be made:

• Legacy support model
• Reference clock source selection
• Process/packaging technology selection
• Power-down requirements (what happens when the cable is NOT attached)
• Test & debug strategy

The key to understand the first bullet point is that USB 3.0 requires a new cable, basically 5 extra wires with differential receive and transmit pairs. The new SuperSpeed mode operates ten times faster than USB 2.0 – at an impressive 5Gb/s. This also requires simultaneous transmit and receive because USB 2.0 is bidirectional and this is where the legacy support comes into play. USB 3.0 must support 480 Mb/s high speed and full speed operation. Some customers think that using their existing USB 2.0 PHY & simply adding a SuperSpeed PHY, simplistically a 5 Gb/s SERDES, is a low risk solution to get to a complete backwardly compatible USB 3.0 implementation.

Not so.

With a completely integrated solution both the SuperSpeed and the USB 2.0 PHY’s come together as a single block. When done right this means that only a single input reference clock, a single external calibration resistor and a single USB 3.0 controller (link layer) is needed. This will handle all four speed modes of USB 3.0 from SuperSpeed to low speed. Also as I explained to the customer, Synopsys passed USB 3.0 compliance with our PHY’s and controllers and we offer a hardware validation platform of the entire solution using the Synplicity HAPS system.

So the only obscene gestures potentially come from a customer trying to figure out how to integrate the USB 3.0 5 Gb/s portion with the USB 2.0 PHY by themselves. 

With some of our USB 3.0 development team, we attended the 20th annual EDN innovation awards ceremony in San Jose. In order to develop this award winning product we blended the expertise of  USB and SERDES, PHY and controller teams, located worldwide, combining USB 2.0 and the emerging USB 3.0  to yield fully functional first silicon using a wire-bond package. That’s right 5 Gb/s through wirebond.

This solution passed all of the USB 2.0 and USB 3.0 interoperable test suites, as well as the electrical tests for both 480-Mb/s and 5-Gb/s operational modes. Resulting in a complete solution, optimized for cost, area, power and functionality—for example, requiring only a single external reference clock input and single external calibration resistor that are shared between the two operational modes.

Kudos to our development team as they are spread across the globe in six locations: Hillsboro, OR; Toronto and Ottawa, Canada; Mt View, CA; India; and Armenia.

Some of our USB 3.0 development team at the EDN awards ceremony

As Jeff Ravencraft puts it “Passing certification is important as it demonstrates that the IP (intellectual property) meets USB-IF interoperability standards and is compliant to the USB 3.0 specification”. And being the president and chairman of the USB Implementers Forum, he should know.

What certification tells you is that the USB 3.0 (or any standards based IP) passed protocol, electrical, and interoperability tests for both SuperSpeed (5 Gb/s) and Hi-Speed 480 Mbps modes. What this means is that you can take the certified USB 3.0 IP and integrate into your 65-nm or 40-nm SoC, comfortable in the knowledge that it will support both USB 3.0 and USB 2.0 speeds.

To get to the certification, or as the title of this post has it “What’s behind certification”, is a thorough verification methodology that ensures functional correctness.

For the physical layer (PHY) of the USB 3.0 in 65-nm or 40-nm, pre-layout verification in terms of device mismatch and Monte Carlo simulations is becoming a poor predictor of performance. This increases the importance of post-layout parasitic extracted simulations due to the systematic variations based on physical changes to the device. Variation due to device size is well understood and Monte Carlo simulations can be extensively used to evaluate the impact of threshold voltage and saturated drain current mismatch.

However, systematic variations based on physical changes to the device can occur during manufacturing, which can include shallow trench isolation (STI) stress, well proximity, optical proximity and phase shift effects (OPC/PSM); and, the time dependent variation – hot carrier injection (HCI). The new methodologies including post-layout verification need to include all the above factors. Also, at these high speeds, there are additional factors to consider in post-layout verification phase, such as package models assuming a worst-case or pessimistic environment and primary and secondary ESD protections.

With high-speed serial interconnects manufactured in 65-nm and 40-nm technologies, test-chips and silicon characterization are integral to the validation methodology. In order to ensure manufacturing robustness, test-chips must be processed using split-matrix lots where critical parameters such as threshold voltage and mobility are varied. Special testing equipment, including high-speed oscilloscopes, data generators, bit-error rate testers, and compliance test sets are traditionally used to verify the quality of the electrical signaling. These will measure the eye-diagram, jitter generation, jitter tolerance, and other electrical parameters necessary for USB 3.0 certification. The challenge is that bandwidths required to accurately measure the high-speed serial links (in the case of USB 3.0) may not be possible with today’s test equipment, or it becomes very expensive in terms of equipment cost, calibration and set-up.

To address this, the new silicon validation methodologies include having direct visibility into the received eye of the high-speed serial interconnect, without using any special testing equipment to show the link performance. This allows the user to measure the actual eye at the receiver and eliminates the need for expensive test equipment and hardware with SMA connectors to measure a link in the lab or in the field.

In addition, the impact of transmitter pre-emphasis and receiver equalization can be evaluated, which provides additional information on link frequency when used in asynchronous system. Validation at the system level and for board fault analysis, IEEE-1149.6 AC JTAG support should also included in this methodology.

So to finish up on Jeff’s comment:

“Certification of IP building blocks is an important step in the evolution of SuperSpeed USB technology, it assures designers that the solution interoperates with existing USB products while providing the speed and power benefits that SuperSpeed USB offers.”

More information can be found on:

http://synopsys.mediaroom.com/index.php?s=43&item=788

Seventeen USB 3.0 enabled products were announced at the Consumer Electronics show (CES) this week in Las Vegas. Named “SuperSpeed” for the 10x speed increase, these products included ASUS and Giga-Byte Technology motherboards, HP and Fujitsu notebook PC’s, internal and external hard disk drives, USB 3.0 to PCI Express add-in cards and USB 3.0 to SATA storage controllers. Many more consumer products and silicon devices benefitting from the 10X speed increase over USB 2.0 are expected to be announced this year.

At the this year’s CES, one of Synopsys’ USB 3.0 and HDMI customers, Displaylink demonstrated how the speed of USB 3.0 enables flawless transmission of uncompressed 1080P high definition video and 3D gaming over USB. 

  

Above is the tabletop demo showing a USB 3.0 Host PC connected to a Buffalo brand USB 3.0 external hard drive and FPGA board containing Displaylink’s proprietary display technology and USB 3.0 and HDMI connections.  Residing next to the blue USB 3.0 cable is a black HDMI cable connected to a 42 inch 1080P Samsung LED LCD.  A variety of high definition movies and display examples were displayed on the LCD TV.

Summer was a very busy time for me both professionally and personally. Looking back now both events were somewhat linked. Work-wise I was busy integrating Chipidea’s analog portfolio into Synopsys’ standards based PHY IP roadmap; personally I was challenged with learning the Waltz for the opening dance of my wedding.

Since May, we’ve been working on the integration of the former Chipidea analog portfolio into our very successful mixed-signal IP business. This meant figuring out an analog IP product roadmap for data converters (ADC’s, DAC’s), audio CODEC’s, video front-ends and touch-screen controllers. In a way, this was a “marriage” between our standards based interconnect roadmap (USB, PCI Express) with analog IP such as data converters that do not necessarily follow a particular standard specification. The goal of an IP company is to leverage as much engineering effort into standard based IP blocks. The good news is that over the past few months we have created a product roadmap for analog IP that not only follows the same principle as our interconnect roadmap but also matches our customer requirements in terms of the next generation of technnology nodes, data converter architectures and high performance audio/video IP.

Since there was an extensive analog IP portfolio existing at 65 nm, the decision was made to enhance the pipeline ADC’s and add wide-band sigma delta architectures to the 40 nm technology roadmap. With audio the goal is to continue enhancing the 96 dB, 103 dB platforms with lower power/area and adding Class D output stages. The video platform will support 3 channel 1080p WUXGA. There’s a couple of excellent introductory papers in our latest DesignWare Technical Bulletin that contain more information:

“Advanced audio drivers” https://www.synopsys.com/dw/dwtb.php?a=advanced_audio_drivers&elq=8e4455bc49944db393a466a7ffc9ec15

and

“Choosing the right architecture for analog-digital conversionin wireless communication broadband IC’s” https://www.synopsys.com/dw/dwtb.php?a=adc_in_wireless&elq=8e4455bc49944db393a466a7ffc9ec15

Oh, so now you’re asking…how were the two events linked? Well, having mastered the standard based waltz with its 1-2-3, 1-2-3 step to Strauss’ Blue Danube, we decided to mix in Punjabi MC rap into our wedding dance. Understanding the bangra rythmns and choreographing them into our waltz we created a new standard, much to the delight of our international audience!