Archive for the 'SATA' Category

Synopsys’ user group (SNUG) attracts about 3000 engineers over the three day event in San Jose. This year we will repeat the very successful “IP Summit” – a day devoted to designers and technology leaders. Topics relevent to today’s design challenges and expert opinions on future directions will be presented in a 60 to 90 minute tutorial format:

- Best practices on implementing memories and libraries

- Designing PCIe 3.0 Express

- RFID tagging technology

- Meeting quality of service for DDR controllers

- Creating an Audio IP subsystem

- Using synthesis tools to improve datapath quality of results

- Integrating USB 3.0

- Integrating MIPI

-The Role of IP in More Moore and More than Moore

Also TMSC’s Dr. Suk Lee  will present “The Impact of Process Migration on IP Design” key note, over lunch.

You’ll have the opportunity to hear from industry experts, ask questions and of course network.

Looking forward to seeing you there.

When: Wednesday March 28
Where: Santa Clara Convention Center

More details: : http://www.synopsys.com/IP/Pages/IPSummit2012.aspx

Tomorrow I’ll be presenting at TSMC’s OIP (Open Innovation Program) on a topic regarding high performance analog and interface IP that is used in the latest smart phones, tablets and also the data centers. The idea of the talk was triggered by an article that I read about how the theoretical limit of Shannon’s Law is being reached and that Moore’s Law can be used to extend this bandwidth limit. What I’m presenting is that using the latest 28 nm and 20 nm technologies high performance analog and interface IP can be developed that can extend Shannon’s theoretical limit. If you cannot attend the talk, here’s the summary.

Extending Shannon's Limit?

What’s causing this bandwidth limit?

Mobile multimedia products such as smartphones and tablets are driving huge bandwidth requirements into the data centers. A rough order magnitude states that one server in the data center is needed to handle the traffic from every 600 smartphones or 122 tablets. By 2015, it is projected that 7.1 billion phones and tablets, will be sending 75 exabytes (one billion gigabytes) of internet traffic. To address these bandwidth limits, Moore’s Law is driving innovation at the system-on-chip (SoC) level with quad-core CPU’s running in excess of 1.5 GHz in 28 nm. In order to get data on and off the SoC, from the application processor to the base-band chip, high performance interfaces are used. Since the design and implementation challenges are significantly greater at 28 nm and below, SoC development teams are looking for ways to meet aggressive product cycles by implementing third party intellectual property (IP) for these interfaces. 

28-nm, 20-nm technology and IP

Being a consumer driven market, cost is a major factor for mobile multimedia products and SoC companies are using economies of scale afforded by 28 nm integration levels to build media processors to fit multiple personal computer and consumer electronic platforms. The interface IP needs include multi-port USB 2.0, USB 3.0, HSIC (high-speed inter-chip) which is derived from the USB protocol, PCI Express Gen. 1, SATA, HDMI Tx (to connect to high definition displays), MIPI CSI/DSI for camera and displays interfaces, Gigabit Ethernet and SD 4.0. Also, smartphone storage will exceed 100 GB in 2012 and this will require both throughput and capacity: USB “sync-n-go”, micro-USB, potentially UFS (universal flash storage) are likely candidates for this type of interface IP. The DRAM bandwidth is growing faster than any market segment: mDDR (mobile DDR) is being replaced by LPDDR2 this year. Audio codec’s and general purpose data converter IPs are also required. The low power variant of 28 nm technology (the POLYSION based LP, or the HKMG HPL) is the preferred choice with a 1.8 V gate oxide. Other important requirements include special power down modes.

On the other end, data centers or cloud computing is driving high-end IP requirements in 28HPM or 28HP processes. The data center backbone will use the 8 Gb/s PCIe 3.0 switches and these are used to connect to multi-channel 10 Gb Ethernet HBA (host bus adapters). The high-speed DDR3 memory interfaces are expected to operate at 2133 Mb/s supporting both RDIMM and LRDIMM – and these will eventually move to DDR4 2013.

How does TSMC’s OIP help in all of this?

TSMC’s Open Innovation Program (OIP) is an integral part of the collaboration between Synopsys and TSMC. For analog/mixed-signal IP this means access to early versions of design kits help reduce the adoption barrier for customers implementing next-generation SoC designs in the advanced process technologies.  By providing IP that meets the rigorous TSMC9000 certification standards, Synopsys and TSMC are enabling our mutual customers to reduce integration risk and system cost, while quickly ramping up into volume production

Booting from a solid state drive (SSD) is much faster than the traditional hard disk drives and this is just one of the many reasons that the SSD’s have become popular in consumer devices. To assist developers of these products, one of our partners Global Unichip (GUC) has developed an SSD reference platform for mobile applications such as netbooks, mobile internet devices (MIDs) and high-speed pen drives. The connection to the netbook is made via the high performance SATA bus as shown below.

The GP5080 reference platform, provides developers with a low power, high data system throughput of more than 120 MB/s in sequential read and over 80 MB/s in sequential write with 4-channel NAND Flash access.

Translated into layman’s language this is bags faster than hard disk drives during booting.

Below is a block diagram of the reference platform

As well as the SATA interface, the GP5080 features a 32-bit ARM7 processor.  This provides firmware capability to improve the SSD’s performance in terms of lifetime and reliability by providing higher computing capability such as a flash translation layer, bad block management, wear leveling algorithm and power fail recycling.

This post describes the impact an IP vendor can have on making improvements to the standardization of a serial bus interface due to the influence of low power/low leakage deep sub-micron CMOS process technologies.   

Serial ATA (SATA) is a high-speed serial bus interface used to transfer data from motherboards to peripheral storage devices, such as optical disk drives, HDDs and solid state disk drives. The SATA interface is being integrated into SoCs for consumer electronic products and enterprise class storage systems.  According to IDC, more than 1.1 billion SATA hard drives have shipped from 2001 to 2008. Last year, SATA captured more than 98% of internal hard disk drive shipments, demonstrating that SATA technology is now used in the vast majority of desktop and mobile personal computers.  

So - there is a lot of SATA out there and it makes sense to develop it as IP.  

Due to this demand, the SATA interface is increasingly becoming available as third party intellectual property (IP) in leading edge deep sub-micron CMOS technologies (65/55 nm and 40/45 nm) to help speed development time and lower costs. The quality, completeness and interoperability of this IP become the key considerations to the SoC integrator.   

Interoperability is a key part of the standardization of SATA interface and a program managed by the SATA-IO http://www.serialata.org/, ensures interoperability across SATA products. The interoperability task is becoming complex and is not only a consideration on the system side but also on the IP developer.   

During testing in our Hillsboro, Oregon labs., we discovered two electrical specifications related to wake-up from sleep mode and out of band signaling that did not reflect the current performance of today’s leading edge CMOS technologies. The SATA testing requirements and specifications for partial exit latency for host applications with spread spectrum-enabled only and the burst and gap width tolerances for out of band signals needed to be updated. The bottom-line was that  the speed and on-chip variations of the low power, low leakage deep sub-micron CMOS technologies posed certain challenges to SATA logo certification for these two specifications. The good news was that having completed silicon evaluation of over hundreds of devices, our SATA experts saw no impact on functionality or interoperability. Therefore our proposal, that was successfully received, to the SATA-IO Working Group was to update the the logo testing requirements.    

Together with the SATA IO Working Group, Synopsys helped to resolve these two issues. The specific details are available to SATA-IO members in the latest version of the Universal Test Document (UTD) 1.4.1. 

SATA Disk Drives That Passed Interoperability