Archive for the 'PCI Express' Category

Synopsys’ user group (SNUG) attracts about 3000 engineers over the three day event in San Jose. This year we will repeat the very successful “IP Summit” – a day devoted to designers and technology leaders. Topics relevent to today’s design challenges and expert opinions on future directions will be presented in a 60 to 90 minute tutorial format:

- Best practices on implementing memories and libraries

- Designing PCIe 3.0 Express

- RFID tagging technology

- Meeting quality of service for DDR controllers

- Creating an Audio IP subsystem

- Using synthesis tools to improve datapath quality of results

- Integrating USB 3.0

- Integrating MIPI

-The Role of IP in More Moore and More than Moore

Also TMSC’s Dr. Suk Lee  will present “The Impact of Process Migration on IP Design” key note, over lunch.

You’ll have the opportunity to hear from industry experts, ask questions and of course network.

Looking forward to seeing you there.

When: Wednesday March 28
Where: Santa Clara Convention Center

More details: : http://www.synopsys.com/IP/Pages/IPSummit2012.aspx

Tomorrow I’ll be presenting at TSMC’s OIP (Open Innovation Program) on a topic regarding high performance analog and interface IP that is used in the latest smart phones, tablets and also the data centers. The idea of the talk was triggered by an article that I read about how the theoretical limit of Shannon’s Law is being reached and that Moore’s Law can be used to extend this bandwidth limit. What I’m presenting is that using the latest 28 nm and 20 nm technologies high performance analog and interface IP can be developed that can extend Shannon’s theoretical limit. If you cannot attend the talk, here’s the summary.

Extending Shannon's Limit?

What’s causing this bandwidth limit?

Mobile multimedia products such as smartphones and tablets are driving huge bandwidth requirements into the data centers. A rough order magnitude states that one server in the data center is needed to handle the traffic from every 600 smartphones or 122 tablets. By 2015, it is projected that 7.1 billion phones and tablets, will be sending 75 exabytes (one billion gigabytes) of internet traffic. To address these bandwidth limits, Moore’s Law is driving innovation at the system-on-chip (SoC) level with quad-core CPU’s running in excess of 1.5 GHz in 28 nm. In order to get data on and off the SoC, from the application processor to the base-band chip, high performance interfaces are used. Since the design and implementation challenges are significantly greater at 28 nm and below, SoC development teams are looking for ways to meet aggressive product cycles by implementing third party intellectual property (IP) for these interfaces. 

28-nm, 20-nm technology and IP

Being a consumer driven market, cost is a major factor for mobile multimedia products and SoC companies are using economies of scale afforded by 28 nm integration levels to build media processors to fit multiple personal computer and consumer electronic platforms. The interface IP needs include multi-port USB 2.0, USB 3.0, HSIC (high-speed inter-chip) which is derived from the USB protocol, PCI Express Gen. 1, SATA, HDMI Tx (to connect to high definition displays), MIPI CSI/DSI for camera and displays interfaces, Gigabit Ethernet and SD 4.0. Also, smartphone storage will exceed 100 GB in 2012 and this will require both throughput and capacity: USB “sync-n-go”, micro-USB, potentially UFS (universal flash storage) are likely candidates for this type of interface IP. The DRAM bandwidth is growing faster than any market segment: mDDR (mobile DDR) is being replaced by LPDDR2 this year. Audio codec’s and general purpose data converter IPs are also required. The low power variant of 28 nm technology (the POLYSION based LP, or the HKMG HPL) is the preferred choice with a 1.8 V gate oxide. Other important requirements include special power down modes.

On the other end, data centers or cloud computing is driving high-end IP requirements in 28HPM or 28HP processes. The data center backbone will use the 8 Gb/s PCIe 3.0 switches and these are used to connect to multi-channel 10 Gb Ethernet HBA (host bus adapters). The high-speed DDR3 memory interfaces are expected to operate at 2133 Mb/s supporting both RDIMM and LRDIMM – and these will eventually move to DDR4 2013.

How does TSMC’s OIP help in all of this?

TSMC’s Open Innovation Program (OIP) is an integral part of the collaboration between Synopsys and TSMC. For analog/mixed-signal IP this means access to early versions of design kits help reduce the adoption barrier for customers implementing next-generation SoC designs in the advanced process technologies.  By providing IP that meets the rigorous TSMC9000 certification standards, Synopsys and TSMC are enabling our mutual customers to reduce integration risk and system cost, while quickly ramping up into volume production

What struck me recently about cloud computing was its similarity to PCI Express virtualization. Here’s a some dialog I’ve been having with one of the foremost experts, the CTO of Virtensys, Marek Piekarski.

The synergies between cloud computing and I/O Virtulization (IOV) are pretty straight forward: cloud computing assumes a complete decoupling of applications from platforms (any application can run on any platform). For that to happen – efficiently – you have to be able to provide an application with just the right mix of CPU performance, connectivity, I/O bandwidth (QoS to be more precise) to clients, storage or other processors as required. That is hard to do with the existing PC-derived server architecture where the I/O capabilities of a server (HBAs, NICs, DAS…) are defined at data center build-time rather than at application run-time. IOV effectively separates all the I/O from the compute part of the servers and allows the above “mix” to be dynamically tuned on demand.

Why PCI Express? It’s the default I/O interconnect in servers today. It in effect defines the boundary between the compute and I/O subsystems in a server. So why would you use anything else? Putting anything else in the way (eg., Infiniband) just adds cost, power, complexity and a bandwidth bottleneck.

Another characteristic of using PCI Express is that we can make the IOV technology completely transparent to the server software. The servers still see standard PCIe NICs and HBAs (albeit those are now virtual rather than physical) and run the same standard I/O vendors’ driver and management utilities. This makes minimises the potential disruption caused introducing IOV (never a good thing in the real world) and also accounts to some extent why you don’t see a “bandwagon” effect. PCIe IOV does not require an “ecosystem” because of this “transparency”. It also makes it a very horizontal technology. It doesn’t just apply to clouds but to all computing platforms today. It is certainly a key enabler for clouds, but I wouldn’t want associated only with clouds.

There’s a much bigger market out there.

To solve the problem of filming Avatar’s virtualized 3D-world where the subjects moved quickly and unpredictably, film-makers used artifical intelligence to select the most appropriate camera angles and shots. In the PCI Express world, a similar concept called virtualization allows multiple operating systems running simultaneously within a single computer to share PCI Express devices. The special interest group, PCI-SIG today announced the latest release of the virtualization specification. Here’s some background on how the virtualized world of PCI Express is created.

Virtual resources act as proxies for physical resources (memories, disk drives and servers) that have the same external interfaces and functions composed from physical resources. A “virtualization intermediary” creates virtual resources and “maps” them to physical resources and provides isolation between virtual resources and this is accomplished through a combination of software, firmware, and hardware mechanisms.

So, imagine applying virtualized devices using PCI Express for a 10 Gb Ethernet backbone.

To keep things simple suppose that we tried to share this connection using physical deployment giving each physical machine access to 5Gb, or half of the available bandwidth, which we will implement with five 1Gig Ethernet adaptors in each machine feeding into a switch that has the actual 10Gig connection to the network.

Obviously this has introduced a considerable amount of additional HW, meaning added cost and, probably more importantly, space and power. But we have also statically partitioned the bandwidth.

Contrast that with an approach that uses virtual deployment of the bandwidth, as in the picture, and you can see that the management of that device can be very fluid and based on the dynamic requirements of each of the consumers of the bandwidth.

More about virtulization can be found on http://synopsysoc.org/theeyeshaveit/?p=33 and

http://www.pcisig.com/specifications/iov/single_root/