Posted by Navraj Nandra on 26th March 2012
The need for embedded multiple time programmable (MTP) non-volatile memory (NVM) IP in advanced process nodes is rapidly increasing as designers integrate more features and functionality into their system-on-chip (SoC) designs. One of the key applications driving the need for MTP in advanced nodes is Near Field Communications (NFC). NFC-enabled smartphones and rapidly on the rise and are forecasted to reach >500M units by 2015, accounting for over 30% of the total mobile device shipments (source: iSuppli). In many cases today, the NFC controller functionality is being implemented in a stand alone SoC that requires small amounts of MTP, but will quickly be integrated into the existing connectivity SoC.
The momentum behind widespread NFC deployment has been growing for several quarters with smartposter demos happening all over the world, including one in Times Square in September, and multiple countries testing NFC for transit applications, including rumors that London will have their entire bus and subway systems NFC capable in time for the 2012 Olympic Games. The Holy Grail of NFC applications is the implementation of a mobile wallet. The Isis (www.paywithisis.com) consortium has brought together mobile operators (AT&T, T-Mobile, and Verizon originally), financial institutions (Chase, CapitalOne, and BarclayCard) and smartphone manufacturers (HTC, LG, Motorola, RIM, Samsung, and Sony Ericsson) to create an ecosystem with the reach to implement a widely adopted, secure mobile wallet system.
SoC designers need to understand the available IP technology on 65- and 40-nm processes so they can choose optimized and reliable solutions for their applications. A webinar on April 12th http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=synopsys_apr1212Â will focus on three main topics:
- Review the key applications and use models that drive the need for embedded MTP NVM IP in advanced process nodes
- Discuss the capabilities and limitations of technologies used to implement embedded MTP NVM IP in advanced process nodes
- Understand how Synopsys aligns the application and market needs to provide embedded MTP NVM IP at advanced nodes with optimized, targeted technology capabilities

Posted in An analog designer speaks!, NVM | No Comments »
Posted by Navraj Nandra on 15th March 2012
Synopsys’ user group (SNUG) attracts about 3000 engineers over the three day event in San Jose. This year we will repeat the very successful “IP Summit” – a day devoted to designers and technology leaders. Topics relevent to today’s design challenges and expert opinions on future directions will be presented in a 60 to 90 minute tutorial format:
- Best practices on implementing memories and libraries
- Designing PCIe 3.0 Express
- RFID tagging technology
- Meeting quality of service for DDR controllers
- Creating an Audio IP subsystem
- Using synthesis tools to improve datapath quality of results
- Integrating USB 3.0
- Integrating MIPI
-The Role of IP in More Moore and More than Moore
Also TMSC’s Dr. Suk Lee will present “The Impact of Process Migration on IP Design” key note, over lunch.
You’ll have the opportunity to hear from industry experts, ask questions and of course network.
Looking forward to seeing you there.
When: Wednesday March 28
Where: Santa Clara Convention Center
More details: : http://www.synopsys.com/IP/Pages/IPSummit2012.aspx

Posted in An analog designer speaks!, DDR, General - mixed-signal IP, NVM, PCI Express, SATA, USB | 2 Comments »
Posted by Navraj Nandra on 3rd March 2012
In preparing for the Synopsys Users Group (SNUG) tutorial on “The Role of IP in More Moore and More than Moore”, I had to present the “dry run” yesterday to my colleagues. So this is what I’m presenting. Known as “more Moore”, high-k metal gate dielectrics, double patterning and finFET’s have extended Moore’s law to 14-nm. Targeting the next generation application processors for tablets and super smart phones, the benefits are performance, lower power and area. Typically at 65-nm and above, “More than Moore” – innovation occurs with integrated sensors and near field communication technologies in applications such as smart-posters and radio frequency identification. In both cases IP is required but has a different design requirement. Innovations such as 3D are also occurring. A detailed technical review of these technology innovations, the design and implementation challenges for analog and physical IP will be presented. I’ll be giving this tutorial on March  28th at  3pm at the Santa Clara Convention Center.

More Moore and More than Moore Technologies
Posted in An analog designer speaks!, Data Converters, DDR, General - mixed-signal IP, HDMI, Low Power, Low Power - Analog Designer's Guide, NVM, PCI Express, SATA, USB | 4 Comments »
Posted by Navraj Nandra on 3rd October 2011
NFC – or Near Field Communication is a technology that allows, amongst many other uses, mobile payment and transportation ticketing using your cell phone. The underlying technology for NFC has been around for quite a while, but until now the supporting ecosystem has been lacking. The most significant development has been the formation of Isis, a collaboration of AT&T, T-Mobile, and Verizon to establish a mobile payment platform that is now being backed by almost all the major handset manufacturers including HTC, LG, Samsung, Motorola, RIM, and Sony Ericsson. The Isis momentum is augmented by a number of other recent announcements from key technology companies. Google just recently released the trial version of Google Wallet and Broadcom has announced a 40nm SoC that supports NFC.

iSupply is forecasting ~55% CAGR in NFC for mobile phones between now and 2015.
 
NFC enabled handsets will create new opportunities for marketing, payment, and data interactions for consumers. At the most basic level, smart posters with embedded NFC tags will allow a passerby to download information on local restaurants, movie trailers, or upcoming events by simply tapping their phone on the poster. Maxim Integrated Circuits recently announced that they will be demonstrating smart poster technology at upcoming conferences and for a period of 4 hours recently, there was an NFC enabled sign demonstration in Times Square.
Moving beyond smart posters is full mobile payment. One of the keys to enabling mobile payment is the creation and implementation of a secure element to provide the necessary encryption technology to satisfy the requirements of the entire ecosystem, including consumers, network operators, and financial institutions. The need for secure elements is being served in two main ways. First, a number of companies, such as Verayo, have taken their proprietary technology and used it to create discrete ICs that can be incorporated into systems such as a SIM card to provide security function. Other companies, including IntrinsicID and Invia among others, are developing their technology to be delivered as IP for integration into larger SoCs.
One common requirement for both smart posters as well as mobile payments is the need for embedded nonvolatile memory. Synopsys DesignWare portfolio offers a range of nonvolatile memory options optimized for NFC requirements for both discrete tags and secure elements (normally developed in analog focused process nodes) and fully integrated secure elements that require implementation in an advanced process node.
To learn more http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=synopsys_oct0511
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Posted by Navraj Nandra on 6th September 2010
So my boss comes into my office late last week and says: “we’re acquiring this company and you’re going to take care of the non-volatile memory business, ’cause its a bit like analog…” Synopsys Completes Acquisition of Virage Logic Corporation: http://synopsys.mediaroom.com/index.php?s=43&item=838
What an embedded non-volatile memory allows you to do is to store on an SoC, encryption keys, unique chip identification numbers, chip or system configuration data and even trim bits for on-chip analog components. The cool thing about this technology is that you can program it multiple times (to change encryption keys or the bios on your system, for example) and there are no special technology processing steps required. It can all be done in a standard CMOS process.
The number of programming cycles and data retention are couple of important considerations when evaluating embededd NVM. For robust automotive type applications a 10-year data retention at 150C is typically expected with about 1,000,000 write-erase cycles over the life of the memory. Yes that’s a million cycles at elevated temperature! Pretty impressive capability to have integrated into your SoC and this technology is already proven with the likes of Analog Devices, Sandisk and Richtek.
As Honda Su, Richtek’s technology executive puts it: “Other factors that attracted us included support for Bipolar/CMOS/DMOS (BCD) processes as it allows us to integrate non-volatile memory IP with high voltage devices in a single IC using a standard CMOS process with no additional masks or processing steps required. A nice additional capability was having all the required high voltage generated from within the IP block itself.”

The graph above summarizes typical applications into the NVM space
I’ll be posting more on this technology in the coming weeks and months but in the mean time here are some product briefs: http://www.synopsys.com/IP/EmbeddedMemories/Pages/AeonNoveaNvm.aspx
Posted in An analog designer speaks!, General - mixed-signal IP, NVM | No Comments »