Archive for the 'Low Power' Category

A couple of years ago we started looking at figuring out how to support analog functions on 28-nm processes, analog functions that had good performance over a wide range of process, voltage and enviromental variations.  One focus area was the audio CODEC. There are three main circuit blocks that limit how much an analog IP scales with process technologies:

• Active amplifiers and resistor ladders: Active amplifiers and resistive ladders are used in a multitude of volume controls and switches that mix different audio sources together. Active amplifier performance is limited by device matching characteristics. Reducing the area of the individual devices negatively impacts the device matching and significantly degrades the active amplifier performance. For this reason, active amplifiers in 28-nm process nodes are not significantly smaller in area than amplifiers with the same performance in 40-nm or 65-nm processes. In order to avoid any noticeable artifacts such as zip noise, the volume gain steps need to be below 1 dB. This requires the resistive ladder to have a large number of taps, which increases the overall area.
• Data converters: Most audio codecs are implemented with sigma-delta ADC and DAC circuits. The noise level in the switched capacitor circuits is inversely proportional to the capacitance. This puts a minimum capacitance value required for a given audio performance requirement, therefore, the capacitor area will not scale with process node. Further complicating matters, as the supply voltage reduces from 2.5 V (or 3.3 V) down to 1.8 V in 28-nm processes, in order to maintain the same dynamic range, the noise level must be reduced. The capacitors must increase in both area and capacitance.
• Output drivers: Large output currents must be delivered with low distortion. In order to support the large output currents needed to drive the headphones and loudspeakers, the output devices must be very large and will not scale with process technology. Similar to the data converter block, and as discussed in more detail below, the output driver circuit area and performance is impacted by the migration from 2.5 V to 1.8 V supplies.

Having evaluated these areas our engineering team were able to suppport these requirements in 28-nm. A more detailed write-up is published on

http://www.eetimes.com/design/audio-design/4238385/Integrating-audio-codecs-in-next-generation-SoCs-for-smartphones-and-tablets?Ecosystem=audio-design

USB is one of those interfaces that you cannot live without. Charging your mobile device or transferring photos, music, powerpoint slides (usually in my case just before an important meeting) is the role of USB. It is the workhorse. It delivers. As files get bigger –  I heard about the Nokia phone that has a 41 megapixel camera http://abcn.ws/xXPiCp - about four times the resolution of my really good camera, the need for a faster USB to transfer these megapixel photos becomes necessary. USB 3.0 is that technology – tens times faster than your current USB. So over the last couple to three years there was lots of talk about USB 3.0 – and finally it happened http://bit.ly/zf99yw .

But what about the previous USB 2.0 generation? In many cases this still is the primary interface in consumer devices and our development and marketing teams at Synopsys have been busy in improving the power, performance and area in the latest 28-nm and 20-nm technologies. In terms of an ecosystem, compliance and interoperability requirements (remember this interface HAS to work), the USB implementers’ forum upped the ante and now require all new USB 2.0 products to demonstrate successful interoperability with various USB 3.0 hosts.  This evolution in the USB 2.0 Hi-Speed logo certification process from requiring successful tests with various USB 2.0 hosts to USB 2.0 and USB 3.0 hosts now just shows how important interoperability with USB 3.0 is becoming.

And it’s becoming more and more mobile oriented…

We call our product USB 2.0 picoPHY. The new features increase battery life and speed recharging in next generation mobile designs, such as smart phones and tablets. Also included is support for  the USB Battery Charger v1.2 standard and addition of low-power features such as aggressive power supply collapsing with high voltage interrupt signaling, and reduced core voltage in suspend mode.

So USB 3.0 is the future but there is plenty of innovation in USB 2.0 left.

Synopsys USB 2.0 test-chips

Silicon results in 28-nm and USB IF certification

TSMC’s announcement this morning about 28 nm reaching volume production lined up with Synopsys’ IP availability on these leading edge nodes. According to TSMC the number of customer 28 nm production tape outs has more than doubled as compared with that of 40 nm – not surprising when companies such as Qualcomm with their Snapdragon platform; both low power and high performance FPGA’s from Altera and Xilinx; and nVidia’s GPU, utilize these technologies. Getting to a production quality level for the 28 nm technologies has posed many challenges to the semicondutor fabs and developing IP on these nodes has required circuit invention to continue following the technology scaling requirements while meeting the manufacturing demands.

From an analog/mixed-signal  design perspective the most interesting challenge was to support the scaling trends that the digital circuits benefit. The challenges can be summarised as: 

• Meeting 28 nm process design rules for manufacturability
• SoC integrators expect analog/mixed-signal IP to follow digital scaling trends – the IP cannot grow in size
• System specs have not changed to reflect lower  (1.8 V) I/O voltages

In order to meet these challenges, new analog/mixed-signal design techniques need to be developed  in order to benefit from technology scaling. Below is an example of an analog to digital converter where, through new design techniques the design has scaled ten times since the original architecture. Calibration techniques (“digitally enhanced analog”) were used to reduce demand on analog features: gain, offset, matching and increase robustness to PVT. And analog techniques such as clock boosting switches to circumvent low supply voltage, while internally processing signals with large voltage swings were used. All of these techniques are applicable to 28 nm.

ADC Scaling Using Design Techniques

 From a system specification perspective, if USB and HDMI are to be integrated on a 28 nm SoC, 5 V compliance requirements must be met – the challenge for the design engineer is to do this using 1.8 V transistors.

Scaling analog/mixed-signal circuits and meeting the “high voltage” system requirements are two of the challenges that must be met in order to support successful implementation of these new 28 nm technologies. That is, the IP needs to work not only on the prototype test-chip but also in production.

Tomorrow I’ll be presenting at TSMC’s OIP (Open Innovation Program) on a topic regarding high performance analog and interface IP that is used in the latest smart phones, tablets and also the data centers. The idea of the talk was triggered by an article that I read about how the theoretical limit of Shannon’s Law is being reached and that Moore’s Law can be used to extend this bandwidth limit. What I’m presenting is that using the latest 28 nm and 20 nm technologies high performance analog and interface IP can be developed that can extend Shannon’s theoretical limit. If you cannot attend the talk, here’s the summary.

Extending Shannon's Limit?

What’s causing this bandwidth limit?

Mobile multimedia products such as smartphones and tablets are driving huge bandwidth requirements into the data centers. A rough order magnitude states that one server in the data center is needed to handle the traffic from every 600 smartphones or 122 tablets. By 2015, it is projected that 7.1 billion phones and tablets, will be sending 75 exabytes (one billion gigabytes) of internet traffic. To address these bandwidth limits, Moore’s Law is driving innovation at the system-on-chip (SoC) level with quad-core CPU’s running in excess of 1.5 GHz in 28 nm. In order to get data on and off the SoC, from the application processor to the base-band chip, high performance interfaces are used. Since the design and implementation challenges are significantly greater at 28 nm and below, SoC development teams are looking for ways to meet aggressive product cycles by implementing third party intellectual property (IP) for these interfaces. 

28-nm, 20-nm technology and IP

Being a consumer driven market, cost is a major factor for mobile multimedia products and SoC companies are using economies of scale afforded by 28 nm integration levels to build media processors to fit multiple personal computer and consumer electronic platforms. The interface IP needs include multi-port USB 2.0, USB 3.0, HSIC (high-speed inter-chip) which is derived from the USB protocol, PCI Express Gen. 1, SATA, HDMI Tx (to connect to high definition displays), MIPI CSI/DSI for camera and displays interfaces, Gigabit Ethernet and SD 4.0. Also, smartphone storage will exceed 100 GB in 2012 and this will require both throughput and capacity: USB “sync-n-go”, micro-USB, potentially UFS (universal flash storage) are likely candidates for this type of interface IP. The DRAM bandwidth is growing faster than any market segment: mDDR (mobile DDR) is being replaced by LPDDR2 this year. Audio codec’s and general purpose data converter IPs are also required. The low power variant of 28 nm technology (the POLYSION based LP, or the HKMG HPL) is the preferred choice with a 1.8 V gate oxide. Other important requirements include special power down modes.

On the other end, data centers or cloud computing is driving high-end IP requirements in 28HPM or 28HP processes. The data center backbone will use the 8 Gb/s PCIe 3.0 switches and these are used to connect to multi-channel 10 Gb Ethernet HBA (host bus adapters). The high-speed DDR3 memory interfaces are expected to operate at 2133 Mb/s supporting both RDIMM and LRDIMM – and these will eventually move to DDR4 2013.

How does TSMC’s OIP help in all of this?

TSMC’s Open Innovation Program (OIP) is an integral part of the collaboration between Synopsys and TSMC. For analog/mixed-signal IP this means access to early versions of design kits help reduce the adoption barrier for customers implementing next-generation SoC designs in the advanced process technologies.  By providing IP that meets the rigorous TSMC9000 certification standards, Synopsys and TSMC are enabling our mutual customers to reduce integration risk and system cost, while quickly ramping up into volume production

At yesterday’s Global Technology Conference in Santa Clara, California, GLOBALFOUNDRIES’ Gregg Bartlett presented a new high performance technology called 28 nm HPP. This is in addition to their gate first HKMG 28 LP, 28 SLP and 28 HP. 

The 28 HPP (HP plus) addresses the growing market for smart mobile devices and high-performance processors requiring more than 2 GHz of processing power. Scheduled to begin risk production in Q4 2011, this technology provides a performance boost of as much as 10% over the company’s current 28 nm High Performance (HP) offering, as well as offering optional ultra-low leakage transistors and SRAMs that extend the application range from high performance into the low power range.

This technology seems to compete with TSMC’s 28 HP(M) – high performance mobile – that was announced at the TSMC symposium in April.

With all these 28 nm process recipes or “HP sauces” on offer, engineers now have plenty of different choices to design high performance and low power devices.

As Dr. Thomas Hoffman from IMEC puts it, high-k metal gate “not only fixes the leakage problem but allows scaling to continue.” Transistors using the standard material used for the gate dielectric — silicon oxynitride (SiON) started seeing excessive leakage current at nodes below 90 nm. The alternative approach using high-k dielectrics can reduce gate leakage significantly, by orders of magnitude. 

There were compatibility issues with standard polysilicon gates that prevented transistors from switching properly at low threshold voltages, therefore high-k gate dielectrics are paired with a metal gate electrodes, hence the term high-k gate metal gate (HKMG). 

Two commercial manufacturing methods have emerged to integrate these materials namely “gate-first” and “gate-last” and are offered by GLOBALFOUNDRIES and TSMC respectively. Eager to capture 28 nm design starts both methods have been compared for both their merits and potential disadvantages. So which one does a design team choose for their 28 nm SoC?

HKMG Gate First, Gate Last

Dr Hoffmann articulates these differences in the above table. Essentially for low power applications gate-first is the better choice. However, for high performance applications the gate-last process with the faster transistors is more appropriate.

With the maximum speed topping out at 1066 Mb/s, mobile applications are driving the DDR roadmap to lower power. This has resulted in a number of different protocols and standards, including: LPDDR2, LPDDR/Mobile DDR, DDR3, DDR3L, DDR3U, and DDR2. These protocols can also be applied to power conscientious server designers, if the speed is not an issue.

Lowering the I/O voltage has a significant impact in the PHY’s power consumption, the rule of thumb is that about 70% of the power comes from the I/O. Therefore LPDDR2 is 1.2 V, DDR3L is 1.35 V and DDR3U is 1.2 V or 1.25 V. For ultra-mobility, the speed can be dropped to 200 MHz and when coupled with techniques using Delay Lock Loop (DLL) bypass modes, these help to reduce the power further. I/O retention modes allow the chip’s power supplies to be shut down completely while a small number of I/Os remain powered on to keep the external SDRAMs in self refresh mode.

So there are quite a few different protocols that enable low power DDR – having all these available in one PHY gives the chip designer the following benefits:

• The final DDR type that is required in the system is software configurable
• Allows one chip design to support multiple applications – very common requirement when a single chip design can cost >>$20M

Synopsys is offering a DDR multiPHY hard macro capable of these six standards.  Hard DDR macro’s offer significant benefits over “soft” PHYs or all digital PHYs such as:

• Quick integration. All pieces of the PHY come from one vendor and have been verified together
• Minimal timing closure problems. Known performance, proven in silicon
• Better performance margins. Lower jitter, better duty cycle and more supply noise rejection
• Area optimized circuits. Each bit path is designed with matched flight times on the data buses

More details on:

http://synopsys.com/dw/ipdir.php?ds=dwc_ddr_multiphy

In the last couple of postings I discussed technology scaling and it’s impact on analog IP.  The point is that like digital gates, analog IP benefits from technology scaling  but with a very different methodology – not using design tools but using different analog architectures: http://synopsysoc.org/theeyeshaveit/?p=242 illustrated USB 2.0 PHY scaling from 180 nm to 28 nm and http://synopsysoc.org/theeyeshaveit/?p=273 showed the example of a dual 10-bit, 80 MHz ADC in an 180 nm technology being five times smaller in 65 nm. So, if we go below 32/28 nm, will we continue to see this size reduction in analog IP?

Is there a size limit?

Our conjecture is that area improvements will happen, but not at the dramatic level as in the 180 nm to 65 nm example above. A couple of reasons for this:

• The advantages of moving from I/O devices to core devices has already been achieved with 65 nm technologies. Moving forward it will become harder and harder to design using sub-1V supplies and the designs will become more complicated in order to yield good performance at those low voltages. Most likely there will be only two transistors stacked with many more placed laterally. 
• The converters are now a very small fraction of the complete SoC area, even if, in some cases, multiple instantiations of the converter are used (for example, MIMO transceivers). Therefore there maybe no market driver/need

Of course, I’m saying this from today’s perspective. With new structures like finFET’s area and power may be further reduced.

Had an interesting discussion with one of our data converter experts with respect to technology node scaling and it’s impact on an analog to digital converter. Manuel’s point is that a run-of-the-mill dual 10-bit, 80 MHz ADC in an 0.18 um technology is five times smaller in 65 nm. This is impressive. And like the USB PHY that I wrote about in my last posting, the size reduction has been achieved by architectural changes. This is what I learned from Manuel:

• Originally, ADC’s were designed using I/O (3.3 V) devices due to the higher voltage headroom that these devices enabled
• Presently all state-of-art ADCs are designed using core (1.2 V or lower) devices
• Although designing high performance converters at core voltage is challenging, it yields substantial gains in terms of maximum sampling rate, power dissipation and, obviously, area

Architectures have evolved significantly. Many design tricks are employed to reduce area. For example, by employing digital calibration schemes, it is possible to relax the performance of the individual analog blocks in  the ADC. This makes those analog blocks (op-amps, comparators, etc) simpler and smaller – and less power consuming.

In the case of dual matched converters, Manuel said that it is possible to be very area effective by re-using a very high sampling rate single channel ADC to convert two channels at half speed. You’ll need to add a special front end stage that sample and holds the two channels in the same instant. An area saving of almost 50% can be achieved.

Note that, as for digital designs, there is a “virtuous cycle”  created by having a smaller design. If the converter is smaller, then the parasitic capacitances that it must drive are smaller and therefore the op-amp that drives them doesn’t need as much higher output drive and the commensurate biasing circuits that go with it are simpler, therefore even more area (and power) can be saved.

I’ll stop at this point. In my next posting, I will explore on how far we can go with this scaling. Where’s the limit? In the meantime you can read more about data coverters on  http://www.chipestimate.com/techtalk.php?d=2009-09-22