Archive for the 'DDR' Category

My last posting http://bit.ly/IFbEV2 drew some questions on whether DDR3L will get into mobile DRAM. I asked our experts and here are their responses. The simple answer is no.  DDR3L is designed to be a PC type DRAM that, due to price and commoditized availability, also suits the embedded applications space of digital home, networking, etc.  As a PC SDRAM, DDR3L relies on an internal DLL to align the read data strobe to the clock (effectively removing the clock insertion delay between clock and strobe). 

This functionality is required in systems that use memory modules with a large number of SDRAM components.  Since mobile applications typically only use one SDRAM per channel, the mobile SDRAMs such as LPDDR2 and LPDDR3 forgo the internal DLL to allow the SDRAM to go into very low power standby states and also dynamically change frequency much faster.  Dynamic frequency change is becoming a critical feature for mobile systems as designers allow the system to tailor the SDRAM clock frequency to the current task at hand.  For example, watching computationally intensive video will require the maximum SDRAM frequency but simple audio playback allows for much lower frequencies to be used conserving precious battery power.  DDR3L is also offered in 4-bit, 8-bit and 16-bit wide configurations whereas the configuration of choice for mobile SDRAMs is 32-bit wide to get as much bandwidth as possible from a single, high capacity SDRAM.  Finally, the DDR3L SDRAM is not offered in a “Package on Package” compatible package that is employed by many mobile designs where the SDRAM is placed directly on top of its host.  For these and a myriad of other reasons, DDR3L is ill suited to mobile applications. 

In fact, DDR3L was conceived as a power reduction effort for the other end of the SDRAM application spectrum, namely servers.  With the average server using more power in the large DRAM array, large server farms are looking for ways to reduce their energy demands and the obvious choice is to look at the DRAM chip which represents the highest volume chip in any server.  Skim a few percent off the DRAM power consumption and you get almost half of that right out of the entire server power budget.

Last week on my trip to Asia, I was asked about the future of mobile DRAM’s, specifically LPDDR and Wide I/O. The mainstream mobile DRAM is LPDDR2 and estimates are that shipments will increase throughout 2012. The 3D multimedia applications will drive requirements for higher bandwidth, the current maximum LPDDR2 bandwidth is only enough to fulfill demand for this year. LPDDR3 is expected to take over in 2013, http://www.dramexchange.com/WeeklyResearch/Post/2/2972.html

The success of another standard, essentially the parallel bus known as Wide I/O, will depend on the maturity of the packaging technology “through silicon via”  (TSV) and adoption of 2.5D/3D integrated circuits. Although Wide I/O shows promise, the challenge comes down to whether it can be made economically and issues such as heat and test can be managed. It may very well be that LPDDR3 is utlized for value orientated products and Wide I/O for the very high end designs that can absorb the extra costs. Work on the next version of Wide IO (v2) has started.  The current Wide I/O version will likely not get much traction, it will all be v2 by the time Wide IO technology becomes adopted in any volume, assuming innovations in packaging technology keep pace and someone figures out the thermal dissipation and testing issues.

LPDDR3 is being designed to meet the needs of the upcoming smartphones and tablets requiring higher bandwidth and offers 6.4 GB/s for dual channel configuration, equating to 12.8 GB/s. It will support both PoP (package on package) and discrete packaging types. LPDDR3 preserves the power-efficient features and signaling interface of LPDDR2, allowing for fast clock stop/start, low-power self-refresh, smart array management, and un-terminated signal lanes.

For LPDDR3, an understanding of the packaging environment is important, even for electrically short implementations, such as Package-on-Package, managing transmission line effects will be critical to successful execution of these challenging interfaces.  System designers will often try to implement the DRAM devices in interconnect environments that exceed the original intentions of the standard. The critical signal integrity effects that impact performance and the interconnect limitations for the target frequency need to be fully understood:

• How transmission line effects limit the performance of the interface and how best to manage these using only source termination
• Crosstalk and its impact on the effective impedance will need to be considered in order to provide effective source termination and interconnect to support all coupling conditions.
• Loading conditions may require the use of pull-up termination
• The bit rate limitations for interconnects that are operated outside of the package-on-package environment and implemented on the printed circuit board using discrete components

The above topics will be described in detail by John Ellis at the JEDEC Mobile Forum on May 10th. Details: http://www.jedec.org/mobile-forum

Synopsys’ user group (SNUG) attracts about 3000 engineers over the three day event in San Jose. This year we will repeat the very successful “IP Summit” – a day devoted to designers and technology leaders. Topics relevent to today’s design challenges and expert opinions on future directions will be presented in a 60 to 90 minute tutorial format:

- Best practices on implementing memories and libraries

- Designing PCIe 3.0 Express

- RFID tagging technology

- Meeting quality of service for DDR controllers

- Creating an Audio IP subsystem

- Using synthesis tools to improve datapath quality of results

- Integrating USB 3.0

- Integrating MIPI

-The Role of IP in More Moore and More than Moore

Also TMSC’s Dr. Suk Lee  will present “The Impact of Process Migration on IP Design” key note, over lunch.

You’ll have the opportunity to hear from industry experts, ask questions and of course network.

Looking forward to seeing you there.

When: Wednesday March 28
Where: Santa Clara Convention Center

More details: : http://www.synopsys.com/IP/Pages/IPSummit2012.aspx

Tomorrow I’ll be presenting at TSMC’s OIP (Open Innovation Program) on a topic regarding high performance analog and interface IP that is used in the latest smart phones, tablets and also the data centers. The idea of the talk was triggered by an article that I read about how the theoretical limit of Shannon’s Law is being reached and that Moore’s Law can be used to extend this bandwidth limit. What I’m presenting is that using the latest 28 nm and 20 nm technologies high performance analog and interface IP can be developed that can extend Shannon’s theoretical limit. If you cannot attend the talk, here’s the summary.

Extending Shannon's Limit?

What’s causing this bandwidth limit?

Mobile multimedia products such as smartphones and tablets are driving huge bandwidth requirements into the data centers. A rough order magnitude states that one server in the data center is needed to handle the traffic from every 600 smartphones or 122 tablets. By 2015, it is projected that 7.1 billion phones and tablets, will be sending 75 exabytes (one billion gigabytes) of internet traffic. To address these bandwidth limits, Moore’s Law is driving innovation at the system-on-chip (SoC) level with quad-core CPU’s running in excess of 1.5 GHz in 28 nm. In order to get data on and off the SoC, from the application processor to the base-band chip, high performance interfaces are used. Since the design and implementation challenges are significantly greater at 28 nm and below, SoC development teams are looking for ways to meet aggressive product cycles by implementing third party intellectual property (IP) for these interfaces. 

28-nm, 20-nm technology and IP

Being a consumer driven market, cost is a major factor for mobile multimedia products and SoC companies are using economies of scale afforded by 28 nm integration levels to build media processors to fit multiple personal computer and consumer electronic platforms. The interface IP needs include multi-port USB 2.0, USB 3.0, HSIC (high-speed inter-chip) which is derived from the USB protocol, PCI Express Gen. 1, SATA, HDMI Tx (to connect to high definition displays), MIPI CSI/DSI for camera and displays interfaces, Gigabit Ethernet and SD 4.0. Also, smartphone storage will exceed 100 GB in 2012 and this will require both throughput and capacity: USB “sync-n-go”, micro-USB, potentially UFS (universal flash storage) are likely candidates for this type of interface IP. The DRAM bandwidth is growing faster than any market segment: mDDR (mobile DDR) is being replaced by LPDDR2 this year. Audio codec’s and general purpose data converter IPs are also required. The low power variant of 28 nm technology (the POLYSION based LP, or the HKMG HPL) is the preferred choice with a 1.8 V gate oxide. Other important requirements include special power down modes.

On the other end, data centers or cloud computing is driving high-end IP requirements in 28HPM or 28HP processes. The data center backbone will use the 8 Gb/s PCIe 3.0 switches and these are used to connect to multi-channel 10 Gb Ethernet HBA (host bus adapters). The high-speed DDR3 memory interfaces are expected to operate at 2133 Mb/s supporting both RDIMM and LRDIMM – and these will eventually move to DDR4 2013.

How does TSMC’s OIP help in all of this?

TSMC’s Open Innovation Program (OIP) is an integral part of the collaboration between Synopsys and TSMC. For analog/mixed-signal IP this means access to early versions of design kits help reduce the adoption barrier for customers implementing next-generation SoC designs in the advanced process technologies.  By providing IP that meets the rigorous TSMC9000 certification standards, Synopsys and TSMC are enabling our mutual customers to reduce integration risk and system cost, while quickly ramping up into volume production

If your designs include DDR subsystems, you have probably heard about DFI and if you have integrated DDR subsystem IP, DDR controllers and PHYs, you are probably fairly intimate with DFI.  In short, DFI is a DDR controller to PHY interface specification.  The intent of the DFI specification is to provide DDR controller and PHY IP designers with a clear description of how the DDR controller must communicate with the DDR PHY and vice versa.  DFI first came about because of the need to support the interface between a DDR controller from one provider and a DDR PHY from another.  DFI 1.0 was the first of the DFI specifications that was developed to support DDR2 followed by DFI 2.0, which included support for DDR3 and then support for LPDDR2 was added with DFI 2.1.  On Monday September 19, a press release was issued announcing the availability of a preliminary release of the DFI 3.0 specification which includes support for DDR4.  This release was supported by the members of the DFI committee of which Synopsys is a contributing member.  You can find a copy of the press release here:  http://www.marketwire.com/press-release/dfi-technical-group-releases-latest-high-speed-memory-controller-phy-interface-specification-1562484.htm 

You can also down load the preliminary DFI3.0 specification at http://www.ddr-phy.org/

Synopsys is a proponent and a driver of the DFI specification because it provides a level of certainty for our IP users when it comes to integration of the DDR subsystem, especially if the user is using the Synopsys DDR controller with another PHY or a Synopsys DDR PHY with a DDR controller IP from another source. 

Synopsys DesignWare DDR protocol controller showing DFI.

Regular readers will have noticed fewer postings lately; my attention focused on integrating, what was until recently, a competing IP product. The Virage acquisition brought an interesting product overlap challenge in terms of the high speed memory interfaces at Synopsys. From the marketing perspective the key questions revolved around which versions to productize since we now had two versions of the DDR digital controller and two versions of the DDR PHY. Of course any decisions had repercussions on the engineering organization, go-to market and sales strategy.

Now with hindsight, having completed our new DDR product roadmap, the integration of the engineering team; the challenge turned out to be great opportunity to bring in the DNA of a company that was making traction in high speed memory interfaces and combining it with our own expertise as an IP provider.

A new DDR controller was released http://synopsys.mediaroom.com/index.php?s=43&item=897 with improvements in latency, performance and lower gate count. The DDR memory controller is user configurable, which allows users to generate a single port DDR controller with all the required features for their particular application.  In addition to basic features, such as bus width, number of ranks and DRAM protocol selection, this release enables users to optimize data throughout and area, with the configurable look-ahead, as well as reduce latency with the optional priority bypass. Several software programmable options to tune the DDR memory controller are offered to meet the needs of the users particular application and traffic.

With respect to the DDR PHY, we were investigating methods to make it easier for our customers to configure, estimate power based on DDR user defined traffic and the result was the DDR PHY Compiler http://synopsys.mediaroom.com/index.php?s=43&item=888.  This is truly a first for DDR PHYs.  The PHY compiler allows customers to use a GUI interface to configure and automatically generate all required files to enable integration of the DDR PHY.  The PHY compiler not only will enable users to configure their DDR PHY, but offer power estimates based on user defined DDR traffic for each supported DDR protocol, a diagram of the PHY even wrapping a corners.  There are over 60 parameters that can be modified to optimize the DDR PHY integration. 

DDR PHY Compiler

In the next few months I’ll be posting more DDR product updates.

Our DDR team at Synopsys had a lot of fun creating a new video and ad campaign for our DDR PHYs.  We call it the “HAAAAAARD PHY” campaign – check out the video at http://www.youtube.com/watch?v=7Ifj90O2N_M to see for yourself. Hopefully you’ll get some chuckles out of it too!

Synopsys DesignWare DDR PHYs are offered as “hard IP” meaning the PHY deliverables are primarily GDSII chip layout and the associated support material such as lef/lib/Verilog/LVS netlist, etc. This is in contrast to other DDR PHYs that are “soft IP” where the PHY is delivered as RTL and the customer must synthesize the “soft PHY”, possibly including other third party DLLs and/or PLLs and close timing. The timing closure problems with soft PHYs become more onerous as the frequency of the DDR interface increases.

 All Synopsys DDR PHYs also include the application specific DDR I/Os that are required for a complete contiguous I/O ring for the DDR PHY. The unique DDR PHY approach from Synopsys allows complete flexibility of the I/O ring layout to balance the I/O ring for small area and good signal integrity. Soft DDR PHYs require that the I/Os be acquired from some other third party IP supplier meaning that as many as 5 different IP vendors can be involved in a soft PHY implementation whereas everything you need for a complete DDR interface can be acquired from Synopsys.

Unlike soft PHY solutions, the DesignWare DDR PHYs hard macro incorporates analog DLL or PLL circuits which enable lower jitter, better duty cycle and an overall superior clock strategy. While soft PHYs often spend over a month on design iterations to close timing and have lower operating frequency ceilings, hard PHYs allow designers to easily meet timing closure and high performance targets, helping to significantly ease the SoC integration effort. As hard IP, a DesignWare DDR PHY embeds the high-speed clock tree and flight time matched data buses, resulting in a more area efficient and lower power design.

We recently demonstrated the Synopsys DDR3/2 PHY and controller test chips live at DesignCon 2010.  The demo features a 32-bit data path operating at 1600Mbps which is probably twice as fast as the DDR channels in the PC or Mac you are using to read this blog.  See how the DesignWare DDR3/2 IP enables automatic timing compensation for voltage and temperature changes, per bit deskew adjustments in the data path, and on-chip capabilities for measuring write and read data eyes.  We also give a sneak peek at DDR3-2133 at the end of the video…

http://www.youtube.com/watch?v=vZ9gdTE7syg

With the maximum speed topping out at 1066 Mb/s, mobile applications are driving the DDR roadmap to lower power. This has resulted in a number of different protocols and standards, including: LPDDR2, LPDDR/Mobile DDR, DDR3, DDR3L, DDR3U, and DDR2. These protocols can also be applied to power conscientious server designers, if the speed is not an issue.

Lowering the I/O voltage has a significant impact in the PHY’s power consumption, the rule of thumb is that about 70% of the power comes from the I/O. Therefore LPDDR2 is 1.2 V, DDR3L is 1.35 V and DDR3U is 1.2 V or 1.25 V. For ultra-mobility, the speed can be dropped to 200 MHz and when coupled with techniques using Delay Lock Loop (DLL) bypass modes, these help to reduce the power further. I/O retention modes allow the chip’s power supplies to be shut down completely while a small number of I/Os remain powered on to keep the external SDRAMs in self refresh mode.

So there are quite a few different protocols that enable low power DDR – having all these available in one PHY gives the chip designer the following benefits:

• The final DDR type that is required in the system is software configurable
• Allows one chip design to support multiple applications – very common requirement when a single chip design can cost >>$20M

Synopsys is offering a DDR multiPHY hard macro capable of these six standards.  Hard DDR macro’s offer significant benefits over “soft” PHYs or all digital PHYs such as:

• Quick integration. All pieces of the PHY come from one vendor and have been verified together
• Minimal timing closure problems. Known performance, proven in silicon
• Better performance margins. Lower jitter, better duty cycle and more supply noise rejection
• Area optimized circuits. Each bit path is designed with matched flight times on the data buses

More details on:

http://synopsys.com/dw/ipdir.php?ds=dwc_ddr_multiphy