Archive for the 'Data Converters' Category

Last week I reviewed a presentation on the impact that clock jitter has on the performance of data converters. What I learnt from our analog design expert Dr. Carlos Azeredo-Leme, is that clock jitter creates uncertainty around the moment when an analog-to-digital converter (ADC) samples the signal. It also adds to conversion noise, and the combination reduces overall system performance.  The problem is getting worse because data converters are getting faster with higher resolutions and they become more sensitive to the quality of the clock. Therefore, clocks must be treated as delicate analog signals requiring minimal disturbances. Pretty interesting stuff! Fortunately, you can also benefit from Dr. Leme’s presentation and ask him questions too by registering on today’s webinar:

http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=synopsys_apr2412&cmp=WEBR-dwip100120-HPE

Dr. Leme will also present:

• Analyzing the effect of jitter on the data converters’ sampling error using the frequency domain and the corresponding phase noise representation of jitter
• Analyzing the jitter characteristics of oscillators and phase locked loops (PLLs), which are the most common clock sources in the system
• Reviewing wireless communications application examples to illustrate the sampling error mechanisms and their impact on the performance of the ADCs
• Presenting typical jitter self-referenced measurements and analyzing their relationships to jitter
• Understanding frequency domain mechanisms that relate jitter to sampling errors enables designers to handle the design trade-offs and to achieve optimal system and data converter performance.

This afternoon, panelists from Cypress Semiconductor, Tanner EDA, IP Extreme, Cadence and Synopsys debated the future of analog/mixed-signal at DesignCon (Santa Clara, California), in the aptly titled “Is It Time for an Analog Comeback” organized and moderated by Brian Bailey. Brian presented the case that today’s analog circuitry has come on-chip and with better tools, questioned whether analog content will increase or will the shrinking geometries cause problems for analog design. Here are some interesting perspectives from the panelists and my thoughts on what they said and as a bonus I’ve added a copy of my slides at the end.

Harold Joseph (Cypress) showed that analog interfaces, “sensor” & general purpose data converters are finding their way into mainstream micro-controllers and other generic digital processing chips. From my perspective we will see more of this as applications ramp-up and mature, for example smart-grid metering and automotive requirements. As these data converters (ADC, DAC) move into the micro-controller, the process nodes required will get smaller. The key is robustness and flexibility in these applications.

Jeff Miller from Tanner EDA presented a good summary of the deep-submicron challenges the impact analog design causing a bottleneck, similar to the points on the first slide below. Solutions to some of these challenges are presented in my slide two.

Warren Savage contradicted the panel by highlighting the OMAP5: complex general purpose digital functions rely on raw performance to differentiate. They start in very advanced nodes to keep power dissipation down and increase functionality.

Although the initial iterations are really general purpose and do not integrate pure analog content, I would say that as the product life-cycle evolves, differentiation is achieved by adding more periphery analog functions. A good example is the application processor that is being merged with the baseband or with the digital TV reception to reduce costs. These ASSPs derivatives include analog in these additional functions.

My panel contribution is captured in the two slides below – there are new challenges in developing analog/mixed-signal in 28-nm and 20-nm but these can be solved with improvements in power, area and performace. The ADC on slide 2 highlights this point.

TSMC’s announcement this morning about 28 nm reaching volume production lined up with Synopsys’ IP availability on these leading edge nodes. According to TSMC the number of customer 28 nm production tape outs has more than doubled as compared with that of 40 nm – not surprising when companies such as Qualcomm with their Snapdragon platform; both low power and high performance FPGA’s from Altera and Xilinx; and nVidia’s GPU, utilize these technologies. Getting to a production quality level for the 28 nm technologies has posed many challenges to the semicondutor fabs and developing IP on these nodes has required circuit invention to continue following the technology scaling requirements while meeting the manufacturing demands.

From an analog/mixed-signal  design perspective the most interesting challenge was to support the scaling trends that the digital circuits benefit. The challenges can be summarised as: 

• Meeting 28 nm process design rules for manufacturability
• SoC integrators expect analog/mixed-signal IP to follow digital scaling trends – the IP cannot grow in size
• System specs have not changed to reflect lower  (1.8 V) I/O voltages

In order to meet these challenges, new analog/mixed-signal design techniques need to be developed  in order to benefit from technology scaling. Below is an example of an analog to digital converter where, through new design techniques the design has scaled ten times since the original architecture. Calibration techniques (“digitally enhanced analog”) were used to reduce demand on analog features: gain, offset, matching and increase robustness to PVT. And analog techniques such as clock boosting switches to circumvent low supply voltage, while internally processing signals with large voltage swings were used. All of these techniques are applicable to 28 nm.

ADC Scaling Using Design Techniques

 From a system specification perspective, if USB and HDMI are to be integrated on a 28 nm SoC, 5 V compliance requirements must be met – the challenge for the design engineer is to do this using 1.8 V transistors.

Scaling analog/mixed-signal circuits and meeting the “high voltage” system requirements are two of the challenges that must be met in order to support successful implementation of these new 28 nm technologies. That is, the IP needs to work not only on the prototype test-chip but also in production.

Tomorrow I’ll be presenting at TSMC’s OIP (Open Innovation Program) on a topic regarding high performance analog and interface IP that is used in the latest smart phones, tablets and also the data centers. The idea of the talk was triggered by an article that I read about how the theoretical limit of Shannon’s Law is being reached and that Moore’s Law can be used to extend this bandwidth limit. What I’m presenting is that using the latest 28 nm and 20 nm technologies high performance analog and interface IP can be developed that can extend Shannon’s theoretical limit. If you cannot attend the talk, here’s the summary.

Extending Shannon's Limit?

What’s causing this bandwidth limit?

Mobile multimedia products such as smartphones and tablets are driving huge bandwidth requirements into the data centers. A rough order magnitude states that one server in the data center is needed to handle the traffic from every 600 smartphones or 122 tablets. By 2015, it is projected that 7.1 billion phones and tablets, will be sending 75 exabytes (one billion gigabytes) of internet traffic. To address these bandwidth limits, Moore’s Law is driving innovation at the system-on-chip (SoC) level with quad-core CPU’s running in excess of 1.5 GHz in 28 nm. In order to get data on and off the SoC, from the application processor to the base-band chip, high performance interfaces are used. Since the design and implementation challenges are significantly greater at 28 nm and below, SoC development teams are looking for ways to meet aggressive product cycles by implementing third party intellectual property (IP) for these interfaces. 

28-nm, 20-nm technology and IP

Being a consumer driven market, cost is a major factor for mobile multimedia products and SoC companies are using economies of scale afforded by 28 nm integration levels to build media processors to fit multiple personal computer and consumer electronic platforms. The interface IP needs include multi-port USB 2.0, USB 3.0, HSIC (high-speed inter-chip) which is derived from the USB protocol, PCI Express Gen. 1, SATA, HDMI Tx (to connect to high definition displays), MIPI CSI/DSI for camera and displays interfaces, Gigabit Ethernet and SD 4.0. Also, smartphone storage will exceed 100 GB in 2012 and this will require both throughput and capacity: USB “sync-n-go”, micro-USB, potentially UFS (universal flash storage) are likely candidates for this type of interface IP. The DRAM bandwidth is growing faster than any market segment: mDDR (mobile DDR) is being replaced by LPDDR2 this year. Audio codec’s and general purpose data converter IPs are also required. The low power variant of 28 nm technology (the POLYSION based LP, or the HKMG HPL) is the preferred choice with a 1.8 V gate oxide. Other important requirements include special power down modes.

On the other end, data centers or cloud computing is driving high-end IP requirements in 28HPM or 28HP processes. The data center backbone will use the 8 Gb/s PCIe 3.0 switches and these are used to connect to multi-channel 10 Gb Ethernet HBA (host bus adapters). The high-speed DDR3 memory interfaces are expected to operate at 2133 Mb/s supporting both RDIMM and LRDIMM – and these will eventually move to DDR4 2013.

How does TSMC’s OIP help in all of this?

TSMC’s Open Innovation Program (OIP) is an integral part of the collaboration between Synopsys and TSMC. For analog/mixed-signal IP this means access to early versions of design kits help reduce the adoption barrier for customers implementing next-generation SoC designs in the advanced process technologies.  By providing IP that meets the rigorous TSMC9000 certification standards, Synopsys and TSMC are enabling our mutual customers to reduce integration risk and system cost, while quickly ramping up into volume production

The latest tablet  announcements are creating lots of excitement but I would like to draw your attention to an emerging technology much closer to home –  in fact coming right out of your regular wall plug. New standards are emerging that will take advantage of all the networks present in your home, these are the electrical power lines running inside your walls, your phone line or the coaxial cables and connect them up in a way that is transparent to you. It appears as one big network. Sounds like a great idea…why hasn’t it been done before?

Well, actually the concept is not new. Different protocols, or standards pushed by many companies, have fought for predominance in the home networking arena. Each uses its own media. For example, the power grid for Power Line Communications, the telephone network for HPNA and the coaxial cable network for MoCA. The figure below shows the home network (G.hn) implementation.

In a typical home several of these networks co- exist, however they are not necessarily physically placed where they are more useful. Everybody has gone through the frustration of finding that the plug in the wall is not where it would be most convenient. This has, in fact, been a major limitation of the adoption of home networking, when compared to wireless.

G.hn, which is being standardized by the ITU, achieves this goal by defining a unified Physical Layer and Data Link Layer that can operate over multiple wire types. Furthermore, this PHY (and other critical blocks in the system) are defined for each wire type, resulting in the ability to outperform the specialized standards for each wire. In other words G.hn unites coax, phone lines and mains (electrical) cabling into a single network capable of hosting multiple HD streams over gigabit bandwidths around the home.

In parallel, the IEEE standardization body is already looking into ways of converging wireline home networking and wireless (WiFi, Power Line and Coax), from the network management perspective. It’s still an open question if this standard (IEEE P1905.1 working group) will also cover G.hn or not.

Apart from convergence, the other key “selling factor” for G.hn is the increased bit rate supported. These two factors place severe requirements in terms of the PHY performance and specifically the data converters. For example, the high data rate (high bandwidth) requires high sampling rates: 200 to 400 MSPS and the harsh, unfriendly, nature of the power grid. This imposes high resolution: 12 to 14-bit while processing these very large bandwidth signals.

I’m happy that Synopsys is participating in these emerging standards, by offering a family of  data converters that addresses exactly the requirements for such systems. This portfolio is made of compact and ultra low power 12-bit 250 MSPS ADCs and 14-bit 400 MSPS DAC which are  ideally suited for broadband communication applications helping to bring intelligence to your home wall plug.

Working on the analog front end for a consumer chip, one of the most important lessons I learnt from a senior engineer at Philips was that you got to figure out how to design analog on a standard digital CMOS process. Nowadays there’s a proliferation of consumer applications ranging from cell phones, computers, TVs and even digital picture frames are incorporating wireless communication transceivers to implement broadband standards such as LTE, WiMAX and WiFi to provide wireless connectivity to the outside world.

In order to save cost and have as many features squeezed in as possible, these SoC’s are manufactured in standard digital CMOS process using feature sizes from 65 nm to 28 nm.

These transceivers rely on an analog interface in the digital baseband processor System-on-Chip (SoC) to connect with the RF block. This analog interface is constantly evolving to adapt to the different communications standards.

Evaluating the specifications of these converters

you can see that performance is not changing significantly. The reason is that these converters are targetted for standard based systems: standards have long lifecycles. Therefore there is no need for faster or higher dynamic range. Power and area become the optimization targets.

The above shows the specification requirements for a communications ADC not changing over ten years but there have been improvements in power and area moving from 180 nm to 65 nm. 

More details on this topic as well as an understanding of the characteristics of the analog interfaces and why they are easy to integrate on the digital baseband SoC will be provided on the techonline webinar: http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=synopsys_sep0910

This webinar will also give an overview of the constituent data converter IP blocks ADC for the receive (RX) path; DAC for transmit (TX) path; and phase locked loop (PLL) and how they can support multiple communication standards. Also providing tips on how these IP blocks can be integrated to create a flexible interface that seamlessly communicates with any RF transceiver block without penalty in the total system power dissipation.