Archive for the 'An analog designer speaks!' Category

Not a topic I usually write about but having a beer with Dr. Yervant Zorian during our recent Synopsys Users’ Group, got me thinking about the challenge of testing embedded IP, that is IP like a USB or DDR that is embedded in one of our customer’s chips. The challenge becomes compounded when multiple IP’s are integrated with different test access strategies, different test interfaces and different mechanisms to describe test patterns. The good news is that Yervant and his team have been looking at this problem  and here is a summary from Gevorg Torjyan.

IP test infrastructure comprises of test hardware and test pattern description

Test hardware might belong but not be limited by one of the following subcategories

a)      Fully integrated BIST with integrated JTAG or IEEE1500 ports

b)      Integrated BIST with access through parallel pins or embedded scan chains

c)       No BIST. BIST is integrated from third party supplier

d)      Digital core that requires wrapping

Test description is delivered at IP level and might be delivered in the form of

a)      Textual description (the worst scenario)

b)      Test bench

c)       Some king of vector format (VCD, CTL, STIL…)

At the same time, due to increasing competition and tighter budget, design teams are required to maintain or downsize their staff. Effectively, they must deliver more with fewer resources. Achieving this goal requires significant productivity improvement.

As a result there is an urgent need of the methodology changes that can help to accelerate assembly of chips and systems through automation.

Proposed approach is based on the EDA infrastructure which will allow to

1. Describe IP test interface and test sequence in the common format
2. Generate IEEE1500 wrappers for each IP block
3. Automated test integration into ASIC RTL
4. Automated pattern porting
5. Generate to level patterns and verification test benches in variety of ATE formats
6. Enable IP test through low cost JATG cable for bench test

Last week I reviewed a presentation on the impact that clock jitter has on the performance of data converters. What I learnt from our analog design expert Dr. Carlos Azeredo-Leme, is that clock jitter creates uncertainty around the moment when an analog-to-digital converter (ADC) samples the signal. It also adds to conversion noise, and the combination reduces overall system performance.  The problem is getting worse because data converters are getting faster with higher resolutions and they become more sensitive to the quality of the clock. Therefore, clocks must be treated as delicate analog signals requiring minimal disturbances. Pretty interesting stuff! Fortunately, you can also benefit from Dr. Leme’s presentation and ask him questions too by registering on today’s webinar:

http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=synopsys_apr2412&cmp=WEBR-dwip100120-HPE

Dr. Leme will also present:

• Analyzing the effect of jitter on the data converters’ sampling error using the frequency domain and the corresponding phase noise representation of jitter
• Analyzing the jitter characteristics of oscillators and phase locked loops (PLLs), which are the most common clock sources in the system
• Reviewing wireless communications application examples to illustrate the sampling error mechanisms and their impact on the performance of the ADCs
• Presenting typical jitter self-referenced measurements and analyzing their relationships to jitter
• Understanding frequency domain mechanisms that relate jitter to sampling errors enables designers to handle the design trade-offs and to achieve optimal system and data converter performance.

The need for embedded multiple time programmable (MTP) non-volatile memory (NVM) IP in advanced process nodes is rapidly increasing as  designers integrate more features and functionality into their system-on-chip (SoC) designs. One of the key applications driving the need for MTP in advanced nodes is Near Field Communications (NFC). NFC-enabled smartphones and rapidly on the rise and are forecasted to reach >500M units by 2015, accounting for over 30% of the total mobile device shipments (source: iSuppli). In many cases today, the NFC controller functionality is being implemented in a stand alone SoC that requires small amounts of MTP, but will quickly be integrated into the existing connectivity SoC.

The momentum behind widespread NFC deployment has been growing for several quarters with smartposter demos happening all over the world, including one in Times Square in September, and multiple countries testing NFC for transit applications, including rumors that London will have their entire bus and subway systems NFC capable in time for the 2012 Olympic Games. The Holy Grail of NFC applications is the implementation of a mobile wallet. The Isis (www.paywithisis.com) consortium has brought together mobile operators (AT&T, T-Mobile, and Verizon originally), financial institutions (Chase, CapitalOne, and BarclayCard) and smartphone manufacturers (HTC, LG, Motorola, RIM, Samsung, and Sony Ericsson) to create an ecosystem with the reach to implement a widely adopted, secure mobile wallet system.

SoC designers need to understand the available IP technology on 65- and 40-nm processes so they can choose optimized and reliable solutions for their applications. A webinar on April 12th http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=synopsys_apr1212 will focus on three main topics:

• Review the key applications and use models that drive the need for embedded MTP NVM IP in advanced process nodes
• Discuss the capabilities and limitations of technologies used to implement embedded MTP NVM IP in advanced process nodes
• Understand how Synopsys aligns the application and market needs to provide embedded MTP NVM IP at advanced nodes with optimized, targeted technology capabilities

A couple of years ago we started looking at figuring out how to support analog functions on 28-nm processes, analog functions that had good performance over a wide range of process, voltage and enviromental variations.  One focus area was the audio CODEC. There are three main circuit blocks that limit how much an analog IP scales with process technologies:

• Active amplifiers and resistor ladders: Active amplifiers and resistive ladders are used in a multitude of volume controls and switches that mix different audio sources together. Active amplifier performance is limited by device matching characteristics. Reducing the area of the individual devices negatively impacts the device matching and significantly degrades the active amplifier performance. For this reason, active amplifiers in 28-nm process nodes are not significantly smaller in area than amplifiers with the same performance in 40-nm or 65-nm processes. In order to avoid any noticeable artifacts such as zip noise, the volume gain steps need to be below 1 dB. This requires the resistive ladder to have a large number of taps, which increases the overall area.
• Data converters: Most audio codecs are implemented with sigma-delta ADC and DAC circuits. The noise level in the switched capacitor circuits is inversely proportional to the capacitance. This puts a minimum capacitance value required for a given audio performance requirement, therefore, the capacitor area will not scale with process node. Further complicating matters, as the supply voltage reduces from 2.5 V (or 3.3 V) down to 1.8 V in 28-nm processes, in order to maintain the same dynamic range, the noise level must be reduced. The capacitors must increase in both area and capacitance.
• Output drivers: Large output currents must be delivered with low distortion. In order to support the large output currents needed to drive the headphones and loudspeakers, the output devices must be very large and will not scale with process technology. Similar to the data converter block, and as discussed in more detail below, the output driver circuit area and performance is impacted by the migration from 2.5 V to 1.8 V supplies.

Having evaluated these areas our engineering team were able to suppport these requirements in 28-nm. A more detailed write-up is published on

http://www.eetimes.com/design/audio-design/4238385/Integrating-audio-codecs-in-next-generation-SoCs-for-smartphones-and-tablets?Ecosystem=audio-design

As we’re devloping HDMI IP, one of the interesting topics in the HDMI community is NG STBs (Next Generation Set Top Boxes) will become dominant in the market in next couple of years. What’s new is that the STB acts simultaneously as a HDMI Sink, an HDMI Source and a HDMI Repeater.  The first application for this new STB being deployed today will provide SKYPE video phone features at the television through the STB, but other applications are planned and coming. The Skype applications requires the STB to overlay both video and sound on top of the external media stream coming in on the HDMI-input from the other HDMI sources in the HDMI cluster.

Synopsys’ user group (SNUG) attracts about 3000 engineers over the three day event in San Jose. This year we will repeat the very successful “IP Summit” – a day devoted to designers and technology leaders. Topics relevent to today’s design challenges and expert opinions on future directions will be presented in a 60 to 90 minute tutorial format:

- Best practices on implementing memories and libraries

- Designing PCIe 3.0 Express

- RFID tagging technology

- Meeting quality of service for DDR controllers

- Creating an Audio IP subsystem

- Using synthesis tools to improve datapath quality of results

- Integrating USB 3.0

- Integrating MIPI

-The Role of IP in More Moore and More than Moore

Also TMSC’s Dr. Suk Lee  will present “The Impact of Process Migration on IP Design” key note, over lunch.

You’ll have the opportunity to hear from industry experts, ask questions and of course network.

Looking forward to seeing you there.

When: Wednesday March 28
Where: Santa Clara Convention Center

More details: : http://www.synopsys.com/IP/Pages/IPSummit2012.aspx

USB is one of those interfaces that you cannot live without. Charging your mobile device or transferring photos, music, powerpoint slides (usually in my case just before an important meeting) is the role of USB. It is the workhorse. It delivers. As files get bigger –  I heard about the Nokia phone that has a 41 megapixel camera http://abcn.ws/xXPiCp - about four times the resolution of my really good camera, the need for a faster USB to transfer these megapixel photos becomes necessary. USB 3.0 is that technology – tens times faster than your current USB. So over the last couple to three years there was lots of talk about USB 3.0 – and finally it happened http://bit.ly/zf99yw .

But what about the previous USB 2.0 generation? In many cases this still is the primary interface in consumer devices and our development and marketing teams at Synopsys have been busy in improving the power, performance and area in the latest 28-nm and 20-nm technologies. In terms of an ecosystem, compliance and interoperability requirements (remember this interface HAS to work), the USB implementers’ forum upped the ante and now require all new USB 2.0 products to demonstrate successful interoperability with various USB 3.0 hosts.  This evolution in the USB 2.0 Hi-Speed logo certification process from requiring successful tests with various USB 2.0 hosts to USB 2.0 and USB 3.0 hosts now just shows how important interoperability with USB 3.0 is becoming.

And it’s becoming more and more mobile oriented…

We call our product USB 2.0 picoPHY. The new features increase battery life and speed recharging in next generation mobile designs, such as smart phones and tablets. Also included is support for  the USB Battery Charger v1.2 standard and addition of low-power features such as aggressive power supply collapsing with high voltage interrupt signaling, and reduced core voltage in suspend mode.

So USB 3.0 is the future but there is plenty of innovation in USB 2.0 left.

Synopsys USB 2.0 test-chips

Silicon results in 28-nm and USB IF certification

This afternoon, panelists from Cypress Semiconductor, Tanner EDA, IP Extreme, Cadence and Synopsys debated the future of analog/mixed-signal at DesignCon (Santa Clara, California), in the aptly titled “Is It Time for an Analog Comeback” organized and moderated by Brian Bailey. Brian presented the case that today’s analog circuitry has come on-chip and with better tools, questioned whether analog content will increase or will the shrinking geometries cause problems for analog design. Here are some interesting perspectives from the panelists and my thoughts on what they said and as a bonus I’ve added a copy of my slides at the end.

Harold Joseph (Cypress) showed that analog interfaces, “sensor” & general purpose data converters are finding their way into mainstream micro-controllers and other generic digital processing chips. From my perspective we will see more of this as applications ramp-up and mature, for example smart-grid metering and automotive requirements. As these data converters (ADC, DAC) move into the micro-controller, the process nodes required will get smaller. The key is robustness and flexibility in these applications.

Jeff Miller from Tanner EDA presented a good summary of the deep-submicron challenges the impact analog design causing a bottleneck, similar to the points on the first slide below. Solutions to some of these challenges are presented in my slide two.

Warren Savage contradicted the panel by highlighting the OMAP5: complex general purpose digital functions rely on raw performance to differentiate. They start in very advanced nodes to keep power dissipation down and increase functionality.

Although the initial iterations are really general purpose and do not integrate pure analog content, I would say that as the product life-cycle evolves, differentiation is achieved by adding more periphery analog functions. A good example is the application processor that is being merged with the baseband or with the digital TV reception to reduce costs. These ASSPs derivatives include analog in these additional functions.

My panel contribution is captured in the two slides below – there are new challenges in developing analog/mixed-signal in 28-nm and 20-nm but these can be solved with improvements in power, area and performace. The ADC on slide 2 highlights this point.

TSMC’s announcement this morning about 28 nm reaching volume production lined up with Synopsys’ IP availability on these leading edge nodes. According to TSMC the number of customer 28 nm production tape outs has more than doubled as compared with that of 40 nm – not surprising when companies such as Qualcomm with their Snapdragon platform; both low power and high performance FPGA’s from Altera and Xilinx; and nVidia’s GPU, utilize these technologies. Getting to a production quality level for the 28 nm technologies has posed many challenges to the semicondutor fabs and developing IP on these nodes has required circuit invention to continue following the technology scaling requirements while meeting the manufacturing demands.

From an analog/mixed-signal  design perspective the most interesting challenge was to support the scaling trends that the digital circuits benefit. The challenges can be summarised as: 

• Meeting 28 nm process design rules for manufacturability
• SoC integrators expect analog/mixed-signal IP to follow digital scaling trends – the IP cannot grow in size
• System specs have not changed to reflect lower  (1.8 V) I/O voltages

In order to meet these challenges, new analog/mixed-signal design techniques need to be developed  in order to benefit from technology scaling. Below is an example of an analog to digital converter where, through new design techniques the design has scaled ten times since the original architecture. Calibration techniques (“digitally enhanced analog”) were used to reduce demand on analog features: gain, offset, matching and increase robustness to PVT. And analog techniques such as clock boosting switches to circumvent low supply voltage, while internally processing signals with large voltage swings were used. All of these techniques are applicable to 28 nm.

ADC Scaling Using Design Techniques

 From a system specification perspective, if USB and HDMI are to be integrated on a 28 nm SoC, 5 V compliance requirements must be met – the challenge for the design engineer is to do this using 1.8 V transistors.

Scaling analog/mixed-signal circuits and meeting the “high voltage” system requirements are two of the challenges that must be met in order to support successful implementation of these new 28 nm technologies. That is, the IP needs to work not only on the prototype test-chip but also in production.